System Level ESD Co-Design
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System Efficient ESD design (SEED) has been an active topic over recent years among ESD designers and the electronics industry as a whole. For this book, Charvaka Duvvury and Harald Gossner along with several contributing authors, have collected an extensive package of knowledge relating to electronic system EMC/ESD co-design. Challenges with EMC/ESD designs vary depending on the industry branch, and by having a specific expertise for EMC testing, semiconductors, automotive and mobile phones business area the book creates both a broad and in deep viewpoint of the SEED methodology. I strongly recommend this book to all electronics system designers to boost their knowledge and to arm them with the tools to predict and prevent ESD or EMC related challenges within future electronic designs. Passi Tamminen, EMC Specialist at Microsoft, FinlandMore details
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Content
List of Contributors xiii
Preface xv
Acronyms xvii
About the Book xxi
1 Introduction 1
Charvaka Duvvury
1.1 Definition of Co-Design 1
1.2 Overview of the Book 2
1.3 Challenges of System Level ESD Protection 2
1.4 Importance of System Level Protection 2
1.5 Industry-Wide Perception 5
1.6 Purpose and Motivation 8
1.7 Organization and Approach 8
1.8 Outcome for the Reader 12
Acknowledgments 12
References 12
2 Component versus System Level ESD 14
Charvaka Duvvury and Harald Gossner
2.1 ESD Threat in the Real World 14
2.1.1 ESD Control 14
2.1.2 ESD Failure Types 15
2.1.3 ESD Protection Areas 16
2.1.4 ESD Stress Models 17
2.2 Component ESD Qualification 17
2.2.1 Component ESD Tests 17
2.2.2 ESD Levels for IC Production 18
2.2.3 Implications for System Level ESD 20
2.2.4 ESD Technology Roadmap 20
2.3 System Level ESD Tests 21
2.3.1 IEC 61000-4-2 22
2.4 ISO 10605 29
2.5 IEC 61000-4-5 31
2.5.1 System Applications 32
2.5.2 Misconceptions and Miscorrelation of Component and System Level Tests 35
2.5.3 Hard Failures Due to IEC Testing 42
2.6 Soft Failures Due to IEC Testing 42
Acknowledgments 43
References 43
3 System Level Testing for ESD Susceptibility 46
Michael Hopkins
3.1 Introduction 46
3.2 Objectives of System Level Testing 47
3.3 Compliance to ESD Standards 47
3.3.1 Legal Compliance Requirements 47
3.3.2 Compliance to Industry Requirements 48
3.4 Testing for Product Reliability 48
3.5 Standards Requirements for System Level Testing 49
3.5.1 IEC 61000-4-2 49
3.5.2 Automotive Standards for ESD 58
3.5.3 Medical Standards for ESD 60
3.5.4 Avionics Standards for ESD 61
3.5.5 Military ESD Standards 61
3.6 Using the IEC Simulator for Device Testing 62
3.7 Cable Discharge (CDE) Testing 63
3.7.1 Shielded Cables 65
3.7.2 Unshielded Cables 65
3.7.3 Modified Transmission Line Pulsers (TLP) for CDE Testing 66
3.8 Evaluation of Test Results 67
3.8.1 Hard Failure Evaluation 67
3.8.2 Soft Failure Evaluation 67
3.9 The Quick Fix vs Root Cause Determination 67
3.10 Determining Root Cause of System Level ESD 68
3.11 Reproducibility of System Level ESD Tests 70
Acknowledgments 72
References 72
4 PCB/IC Co-Design Concepts for SEED 74
Harald Gossner and Charvaka Duvvury
4.1 On-Chip System ESD Protection 74
4.1.1 HBM and CDM vs IEC 74
4.1.2 TLP Characterization 76
4.1.3 TLP Correlation Issues 78
4.2 Off-Chip ESD Protection 79
4.3 Concept of PCB/IC Co-Design 82
4.3.1 On-Chip IEC Protection Solutions 84
4.4 Introduction to System Efficient ESD Design 84
4.4.1 Design Methods for SEED 90
4.4.2 Basic Simulations using SEED 91
4.4.3 USB Design using SEED 94
4.5 Characterization for Hard Failures 97
4.6 Simulation of System Level ESD Discharge Paths 98
4.6.1 Simulation Approach 98
4.6.2 Tools 101
4.6.3 ESD Model Types 103
4.6.4 Extraction of PCB Paths 104
4.6.5 Models of PCB Devices 104
4.6.6 Characterization of IO Cells 106
4.6.7 Power Clamp Models 112
4.6.8 Model for Stress Waveform 114
4.7 Characterization of Soft Failures 116
4.7.1 Purpose and Basic Concept 116
4.7.2 Pin Specific Soft Failure Characterization 120
4.7.3 Soft Failures Related to Signal Integrity Problems 123
4.8 Summary of SEED Characterization 125
Acknowledgments 126
References 127
5 Hard Failures and PCB Protection Devices 129
Robert Ashton
5.1 Introduction 129
5.2 ESD Damage to ICs 129
5.3 Protection Methods 130
5.3.1 Classification of TVS Devices 133
5.4 Characteristics of Protection Devices 134
5.4.1 Current Limiting Devices 134
5.4.2 TVS Properties in Their Off-State 135
5.4.3 Protection Properties of TVS Devices 137
5.5 Types of Protection Devices for ESD 142
5.5.1 Silicon Based TVS Devices 143
5.5.2 Metal Oxide Varistors 154
5.5.3 Polymer Voltage Suppressors 155
5.5.4 Gas Discharge Tubes 156
5.5.5 Spark Gaps on PCBs 158
5.5.6 Thyristor Surge Protection Devices 159
5.5.7 Ferrite Beads 159
5.5.8 Passive Components 161
5.5.9 Common Mode Filters 162
5.6 Primary and Secondary Protection 163
5.7 Evaluating IC Pins 164
5.8 Choosing ESD Protection Devices 164
5.8.1 Coordination between TVS Device and Sensitive Nodes 165
5.9 Summary 167
References 167
6 Soft Failure Mechanisms and PCB Design Measures 169
David Pommerenke and Pratik Maheshwari
6.1 Introduction 169
6.2 Are HBM, CDM, MM, and Latch-Up Results Meaningful Soft Failures? 171
6.3 Classification of Soft Failure Modes 173
6.3.1 In-Band/Out-of-Band with Respect to Voltage 174
6.3.2 In-Band/Out-of-Band with Respect to Pulse Width 175
6.3.3 Local vs Distant Errors 176
6.3.4 Amplified/Non-amplified Soft Failures 176
6.4 Optimized System Level Testing 178
6.5 Soft Failure Characterization Methods 182
6.5.1 Susceptibility Scanning 183
6.5.2 Current Spreading Reconstruction 190
6.5.3 Local Injection 191
6.5.4 Software-Based Methods for Soft Failure Analysis 201
6.6 Soft Failure Examples 205
6.6.1 Example 1: Soft Failure Caused by Field Injection on a DUT (Mini Photo Frame) 205
6.6.2 Example 2: PLL Disturbance Measurement 207
6.6.3 Example 3: Direct Field Coupling on the USB Data Bus 212
6.6.4 Example 4: Direct Injection on the MIPI Bus Interface 215
6.7 Countermeasure Examples 216
6.7.1 Divert Current 216
6.7.2 Filtering 217
6.7.3 Shielding 217
6.7.4 Secondary ESD Avoidance 218
6.7.5 Improved Connector-Cable Shield Connection 218
6.7.6 Enclosure to Connector Shield Junction 218
6.7.7 Firmware 218
6.7.8 Reducing Crosstalk 219
6.7.9 Reduce ESD Current by Resistance 220
6.7.10 Avoid ESD 222
6.8 The Way Forward 223
Acknowledgment 230
References 231
7 ESD in Mobile Devices 234
Matti Uusimäki
7.1 Introduction 234
7.2 ESD Energy Path in Mobile Device 234
7.3 ESD Generation Examples on a Large Scale 239
7.3.1 Large Machines Generating Charges to Their Isolated Bodies 239
7.3.2 Tribo-Electric Series 240
7.3.3 Charge Generated by a Person Inside a Car 240
7.3.4 The Charge Generated to Mobile Device by Accident in Grounded System 241
7.3.5 Alternative Discharging Paths at Connection Moment 244
7.3.6 Charge Behavior at Insulator Surface 244
7.3.7 Example of Consumer Level Charge Generation with Simple Device 246
7.4 Relation between Electrostatic Discharge Immunity Test and Real-World Discharge Waveforms 248
7.5 Laboratory Test Methods 248
7.6 Fast ESD and Slow ESD Concepts 249
7.7 Fast-ESD and Slow-ESD in a Mobile Device 250
7.7.1 Example of Ground Level Bounce Relative to an External Module 251
7.8 Isolating a Mobile Device 252
7.8.1 Example 1: Material Thickness 252
7.8.2 Example 2: Solid Glue 253
7.8.3 Example 3: Positioning Holes in a Rubberized Key Mat 255
7.8.4 Example 4: Induced Electric Field 255
7.9 Shielding a Mobile Device 257
7.10 Orientation Effects on ESD Path 259
7.10.1 ESD Path Example: Phone Face Up on Table 259
7.10.2 ESD Path Example: Phone Face Down on the Table 263
7.11 ESD Design in Practice 264
7.11.1 Grounding Challenges in Practice 264
7.12 PCB Layout Considerations of Metal Shielding "Cans" 267
7.12.1 Components Near the Edge of the Shield 268
7.13 ESD Protection for Cable Interfaces 269
7.13.1 Cable Placement and Common Mode Current in a Mobile Device 270
7.13.2 Localizing Noise Current with Alternate Cabling Placement 274
7.13.3 Cable Interface Protection Components 275
7.14 Common Mode Impedance Concerns for Layout 280
7.14.1 Common Mode Impedance Challenges in the Grounding Paths 280
7.14.2 Signals with Shared Common Mode Impedance 280
7.14.3 Isolating Signals with Shield Grounded to Internal PCB Layers 282
7.14.4 Simulated Example of Ground Impedance Effect on ESD/EMI Filter Performance 283
7.14.5 ESD Protection on Stacked Chips 283
7.14.6 Layout Concerns around the Periphery and PCB Cutouts 285
7.15 ESD and Software Considerations in Mobile Devices 287
7.15.1 Role of Software in EMC and ESD Design 287
7.15.2 Signal Sensitivity to ESD Examples 288
7.15.3 Delayed Effects on Software from ESD Events 290
7.16 Software Versions Utilized in Early ESD Immunity Testing 291
7.17 Conclusion 292
References 292
8 ESD for Automotive Applications 294
Wolfgang Reinprecht
8.1 Introduction and Historical Aspects 294
8.1.1 Why Do Automotive Components Require High ESD Levels? 294
8.1.2 Field Return Rate of Automotive Products due to System Level ESD Events 296
8.1.3 ESD Related Field Returns Because of Incomplete Specification or Missing System Protection 297
8.2 Automotive Components 299
8.2.1 Communication Systems CAN, LIN, FlexRay 299
8.2.2 Power Supply Systems as DCDC Converter, Alternator, LDO 303
8.2.3 Sensors and Sensor Interfaces 304
8.2.4 Keyless Entry/Go with Components Exposed to Human Touching/Handling 311
8.2.5 Power Steering, Drive by Wire, Gearbox, Hybrid Systems, Recuperation 313
8.2.6 LED Lights, Entertainment, Navigation, and Audio 313
8.3 Design Constraints, Operating Voltage, and Overvoltage Tolerance 315
8.3.1 "Normal Overvoltage Range": 18 V into 5 V/3 V/1.8 V 315
8.3.2 Load Dump 315
8.3.3 Loss of Ground, Dual Polarity, and Reverse Polarity 317
8.3.4 EMC Tolerance versus ESD Robustness (Fast Transients) 319
8.3.5 Leakage Current versus ESD Robustness (Pre-Pulse Voltage) 320
8.3.6 Latch-Up-Free ESD Protection versus Snapback Devices 321
8.4 On-Board ESD Protection and Internal ESD Protection 324
8.4.1 Characterization Methods to Get Relevant Data for External ESD Devices 324
8.4.2 ESD Design Window Using External Protection Elements (TVS) 324
8.4.3 Optimizing On-Chip ESD Protections to Match Board Level Protection 324
8.4.4 On-Board Ground Shift due to System ESD Events 325
8.4.5 Secondary Effects as Transient Disturbances to "Internal" Pins (Lateral Coupling) 326
8.4.6 Pin Placement, External Passive Components, and Board Layout Constraints 328
8.5 Verification and Qualification 329
8.5.1 Safe Operating Area Check to Verify Overvoltage Tolerance 329
8.5.2 ESD Design Rule Check to Verify ESD Concept and Constraints 330
8.5.3 ESD Tests on Chip Level HBM/CDM 331
8.5.4 TLP Characterization of Product to Meet SEED 331
8.5.5 System ESD Tests on Board Level up to the Level of Failure 331
8.5.6 No-Gos in Terms of ESD Design 332
8.6 Conclusion 332
References 333
9 Future Applications of SEED Methodology 334
Harald Gossner and Charvaka Duvvury
9.1 Refinement of Models 334
9.2 Limitations of Simulation and Beyond 337
9.2.1 Relation of SEED to System ESD Tests 337
9.2.2 Outlook to a Comprehensive Design Verification 341
9.3 Advances toward High-Speed Systems 342
9.3.1 USB and HDMI Challenges 343
9.4 Issues and Challenges of System Protection 345
9.4.1 USB 2.0 versus USB 3.0 345
9.4.2 USB 2.0/3.0 versus HDMI 346
9.4.3 Automotive Technologies 346
9.4.4 IC Package Technologies 347
9.4.5 PCB Technologies 347
9.4.6 Optical Interfaces 348
9.4.7 Polymer Material Applications 348
9.5 Benefits for Next Generation Systems 349
9.5.1 Harmonized Approach for Component to System Protection 349
9.5.2 IEC Specification Requirements 350
9.5.3 Cost of System Protection 351
Acknowledgments 351
References 351
10 Co-Design Trade-Offs: Balancing Robustness, Performance, and Cost 353
Jeffrey C. Dunnihoo
10.1 Co-Designing across Functional and Corporate Boundaries 353
10.1.1 Component (Factory) versus System (End User) ESD Issues 353
10.1.2 Probabilities and Uncertainties of System ESD Costs 354
10.1.3 Bounded and Cumulative ESD Failure Probability 355
10.1.4 Product and Organizational Response to ESD Failure 357
10.1.5 The Reality of the "Real Cost of ESD" 358
10.1.6 Co-Designing a Solution 358
10.2 ESD Goals and Constraints 359
10.2.1 The Co-Design Gamut 359
10.2.2 ESD Margin Requirement Based on Unknown Probabilities 360
10.2.3 Extreme and Abusive Users 361
10.2.4 Ignoring the "Long Tail" Events 363
10.2.5 Capturing Quantitative System Fault Data 364
10.2.6 ESD Sousveillance 364
10.2.7 Beyond ESD Sousveillance 365
10.2.8 Vulnerabilities in the Meantime 365
10.3 Costs of System and Component ESD Susceptibility 366
10.3.1 Poor User Experience 366
10.3.2 Quantifying User Experience 367
10.3.3 Failure Analysis and Customer Return Costs 367
10.4 Costs of Improving System and Component ESD Robustness 369
10.4.1 Component Costs 369
10.4.2 Reduced Profit Margin 370
10.4.3 Reduced Performance 370
10.4.4 Co-Design Cost Allocation Example 371
10.4.5 Alternative Cost Reductions with Performance Enhancement 372
10.4.6 Increased Time-to-Market and Negative TVS Pricing 375
10.5 Defining the Interaction and Trade-off Matrix 376
10.5.1 Performance 376
10.5.2 Price 377
10.5.3 Robustness 377
10.6 Assigning the Costs of Failure Criteria 378
10.7 System Development Triangle Co-Design Contributions 379
10.7.1 Function Vendor Partitions (CPU, ASIC, Interface Device) 380
10.8 Product Planning Guidelines 380
10.8.1 Set Realistic Robustness Goals Early 380
10.8.2 Responsibilities of the Product Design Team 381
10.8.3 Responsibilities of the Product Testing and Qualification Team 381
10.8.4 Responsibility for Line Returns from Manufacturing 381
10.8.5 Responsibility for Field Returns from the Customer 381
10.8.6 Organizational Interaction with Vendors 381
10.9 Validating Co-Design Trade-off Decisions 382
10.9.1 Historical Data Availability 382
10.9.2 Difficulties of Cost Identification and Assignment 383
10.9.3 Dangers of the "Keep Your Head Down" Mentality 384
10.9.4 Balancing Low-Level Problems with High-Profile Exposure 385
10.10 Conclusions on Co-Design Economics 387
References 387
Glossary 389
Index 391
Acronyms
ADB Android debug bridge ADS Advanced Design System AEC Automotive Electronics Council AMR absolute maximum rating ANSI American National Standards Institute ASIC application specific integrated circuit ASIPT application specific integrated passiveT ASP average selling price ASTM American Society for Testing and Materials ATE automated test equipment AVL approved vendor list BCI bulk current injection BER bit error rate BGA ball grid array BOM bill of materials BSOD blue screen of death CAN controller area network CBE charged board event CCE charged cable event CCTLP charge coupled transmission line pulse CDE cable discharge event CDF cumulative distribution function CDM charged-device model CFB chip ferrite bead CM contract manufacturer CMC common mode choke CMF common mode filter CMOS complementary metal oxide semiconductor CO central office COTS commercial off-the-shelf CPE customer premises equipment CPU central processing unit CRC cyclic redundancy check dB decibel dBm decibel-milliwatt DC direct current DDR double data rate DIP dual inline package DMOS double-diffused metal oxide semiconductor DPI direct power injection DSP digital signal processing DUT device under test DVI digital visual interface ECU electronic control unit EDA electronic design automation EFT electrical fast transients EM electromagnetic EMC electromagnetic compatibility EMI electromagnetic interference EMMI emission microscopy EOS electrical overstress EPA ESD protected area eSATA external serial advanced technology attachment ESD electrostatic discharge ESDA Electrostatic Discharge Association ESR equivalent series resistance EU European Union EUT equipment under test FA failure analysis FB ferrite bead FFT fast Fourier transform FM frequency modulation FTC Federal Trade Commission GDT gas discharge tube GCNMOS gate coupled n-channel metal oxide semiconductor GGNMOS grounded gate n-channel metal oxide semiconductor GND "ground" - negative voltage supply GPIO general purpose IO GPU graphic processing unit GRP ground reference plane HBM human body model HCP horizontal coupling plane HDMI high definition multimedia interface HMM human metal model HSS (HSSL) high speed serial link IBIS input/output buffer info specification IC integrated circuit ID identification IDDQ component quiescent supply current IEC International Electrotechnical Commission IMD inter-modulation distortion IO input/output IP intellectual property IPR intellectual property rights ISO International Organization for Standardization IT information technology IT2 failure current under ESD conditions JEDEC Joint Electronic Devices Engineering Council JEITA Japan Electronics and Information Technology Industries Association LC inductor/capacitor network LCD liquid crystal display LDO low drop out (voltage regulator) LED light emitting diode LIN local interconnect network LU latch-up LVDS low voltage differential signaling MEMS microelectromechanical system MID molded interconnect device MIL-HDBK Military Handbook Mil-PRF Military Performance Specifications Mil-STD Military Standard MIPI mobile industry processor interface MM machine model MOSFET metal oxide semiconductor field effect transistor MOV metal oxide varistor NF noise frequency OBD on-board diagnostics ODM original design manufacturer OEM original equipment manufacturer OMAP Open Media Applications Platform OTG on-the-go PCB printed circuit board PERC programmable electrical rule check PHY physical layer PICC proximity IC cards PLL phase locked loop PN silicon PN junction POST power-on self tests PVS polymer voltage suppressor RC resistor/capacitor network RF radio frequency RH relative humidity RLC resistor/inductor/capacitor network RP residual pulse RPS residual pulse stress RX receiver SATA serial advanced technology attachment SAW surface acoustic wave SCR silicon controlled rectifier SD secure digital (memory card format) SERDES serializer/deserializer SIM subscriber identity module SiP system-in-package SMA sub-miniature version A SMD surface mount device SMT surface mount technology SOA safe operating area SoC system-on-chip SoF start of...
