Preface

In the semiconductor industry, the key term CMOS stands for "Complementary Metal Oxide Semiconductor". This is one of the most popular technologies in the integrated circuits (ICs) design industry and it is broadly used today to form integrated circuits (ICs) in numerous applications. CMOS technology used for design and development of integrated circuits (ICs) that are widely used in digital circuits. Today's computer memories, CPUs, and cell phones make use of this technology due to several key advantages. In CMOS technology, both n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) are used together in a complementary way to form a digital logic gate. The combination of both types of MOSFETs provides better power efficiency and noise immunity compared to other technologies.

As conventional CMOS technology scaling results in smaller and smaller transistor sizes, existing CMOS technology starts to encounter certain fundamental physical limitations. These limitations can potentially result in drastic reduction in performance and energy efficiencies of these transistors, which could make it untenable to continue scaling them. This in turn, would severely limit the benefits of further innovations in IC design. In this scenario, there have been several alternatives proposed at the device level. However, each of these devices comes with varying energy-performance tradeoffs and optimal design points in comparison to CMOS technology. This is the dominant semiconductor technology for microprocessors, microcontroller chips, memories like RAM, ROM, EEPROM and application-specific integrated circuits (ASICs). It is also used in various applications, such as sensors, image processing, and wireless communications. The conventional CMOS technology faces physical limits (short-channel effects, power density) as transistors shrink, requiring new physics and materials to continue performance improvements beyond traditional scaling.

The post-CMOS technologies explore alternatives and complements to traditional silicon CMOS for future computing. It focuses on new materials (2D materials, nanotubes), devices (TFETs, spintronics, memristors), and integration (photonic, neuromorphic, 3D stacking) to overcome CMOS scaling limits, enabling lower power, higher speed, and novel functions like in-memory computing or quantum systems. The key areas include Tunnel FETs, Graphene/CNTs, Spintronics, Photonics, Topological Materials, and Molecular Electronics, often used in hybrid systems with CMOS. Various beyond-CMOS device technologies including tunneling FET (TFET), hybrid phase transition FET (HyperFET), carbon nanotube FET (CNTFET), silicon nanowire FET (SiNWFET), symmetrical tunneling FET (SymFET), phase-change memory (PCM), spin-transfer torque magnetic tunnel junction (STT-MTJ), resistive random access memory (RRAM) have been considered.

The shrinking of transistors to dimensions below 100 nm enables hundreds of millions transistors to be placed on a single chip. The increased functionality and reduced cost of large variety of integrated circuits and systems has brought its own benefit to the end users and above all the semiconductor industry. A low cost of manufacturing, increased speed of data transfer, computer processing power and the ability to accomplish multiple tasks simultaneously are some of the major advantages gained as a result of transistor scaling. The packing density of IC on microelectronics roughly estimated with the help of Moore's Law (an empirical compact mathematical formulation; In this empirical formula N is the number of transistors per chip, F is the minimum feature size, D is the chip area, and PE is transistor packaging efficiency measured per minimum feature area). This empirical formula plays a n crucial for observation on the rate of growth of semiconductor technology. Post CMOS FET refers to filed effect transistor that are being explored as potential future digital logic technologies beyond the current limits of CMOS technology, addressing challenges like scaling and performance. Transistor scaling is a fundamental concept in today's electronics era, driving significant exponential growth in power-efficient technology. This book explores the essential concept and characteristics of CMOS devices and emerging semiconductor technologies that play a crucial role in the industry. It presents a comprehensive yet accessible approach, aiming to deepen understanding of semiconductor scaling and characterization. It is specifically for young researchers, engineers, and students, providing a better understanding of recent developments for the semiconductor inductory.

Nowadays, integrated circuits are realized using CMOS technology. However, the demand for ever smaller, more efficient circuits is now pushing the limits of CMOS. The post-CMOS refers to the possible future digital logic technologies beyond the CMOS scaling limits. The demand for ever smaller and portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nano-FET devices including carbon nanotube transistors, graphene transistors, and tunnel transistors, junctionless FETs, FeFETs, NCFETs, collectively called post-CMOS devices are emerging that could replace the traditional and ubiquitous silicon transistor.

In Chapter 1, the transition from single-gate to multigate field-effect transistors (MG-FETs) represents an important evolution in semiconductor technology, aiming to improve device performance and manage the challenges posed by further miniaturization of components. The multigate field-effect transistors offer significant advantages in several important applications, where ultra-low power consumption, energy efficiency, and low voltage operation are crucial. While they may not yet fully match the drive currents and switching speeds of conventional MOSFETs in all scenarios, their unique operational characteristics make them highly valuable in specific applications, especially as the demand for power efficiency and performance at low voltages solutions grows. Recently, junctionless LMG-FETs (JLMG-FETs) are propped as an advanced class of transistor design to overcome the conventional MG-FET challenges and provide better scalability behavior and low elaboration cost. They are unlike conventional FETs, junctionless FETs do not have p-n junctions. Instead, the entire structure is uniformly doped, simplifying fabrication and enhancing control over channel body. By eliminating junctions and leveraging multigate architectures, these devices offer enhanced electrostatic control, and improved scalability. However, further improvements regarding the analog parameters should be performed in order to understand the impact of each design parameter on the device performances for both double-gate and gate-all - around (GAA) FET structures. In this context, in chapter 1 the scaling capabilities of the JL-MG-FETs has been investigated. To do also, extensive 2D numerical simulations are conducted using Silvaco commercial tool to model the behavior of JL-DG and GAA MOSFETs including the effect of high-k material as a gate-oxide on the subthreshold properties and drain current. A detailed analysis and simulations of their scaling capabilities will be presented and all results will be discussed. By leveraging 2D numerical simulations, our aim is to gain valuable insights into the scaling capabilities and performance benefits of JL-DG and GAA MOSFETs, paving the way for next-generation low-cost nanoscale semiconductor devices.

In Chapter 2 due to high power and high speed applications, high electron mobility transistors (HEMT) have been the area of focus for many research groups in recent years. Compared to conventional field effect transistors (FET), HEMT devices have demonstrated superior performance considering the operational frequency, output power density, and power added efficiency. High electron mobility transistor (HEMT) technology, considerable performance improvements have been brought to the fields of power electronics, radio frequency applications, and high-speed digital circuits. GaN-based complementary metal oxide semiconductor (CMOS) technology combines the wide-band gap characteristics of GaN with the low static power consumption advantages of CMOS, showing significant potential in promoting the development of integrated circuits (ICs). In recent years, numerous research organizations have focused on high electron mobility transistors due to their high power and speed applications, which provide a wide range of applications in electronics, optical and thermal properties. A comparison of field effect transistors with conventional HEMTs reveals that field effect transistors enhance power added efficiency, power density, and operating frequency. Materials into randomly and vertically layered heterostructures. The recently reported vapor phase development of 2D materials offers the path for directly constructing vertical and lateral heterojunction. This study provides insights into layered 2D heterostructures, as well as a brief introduction to 2D material and heterostructure preparation methods. These remarkable 2D heterostructures offer a wide range of possible applications.

In Chapter 3, the nanosheet field-effect transistor (NSFET) represent a transformative advancement in semiconductor technology, addressing the challenges of traditional scaling limits while delivering enhanced performance for...