Microprocessor 4
Core Concepts - Software Aspects
1st Edition
Published on 3. December 2020
256 pages
978-1-119-80195-5 (ISBN)
Description
Since its commercialization in 1971, the microprocessor, a modern and integrated form of the central processing unit, has continuously broken records in terms of its integrated functions, computing power, low costs and energy saving status. Today, it is present in almost all electronic devices. Sound knowledge of its internal mechanisms and programming is essential for electronics and computer engineers to understand and master computer operations and advanced programming concepts. This book in five volumes focuses more particularly on the first two generations of microprocessors, those that handle 4- and 8- bit integers. Microprocessor 4 - the fourth of five volumes - addresses the software aspects of this component. Coding of an instruction, addressing modes and the main features of the Instruction Set Architecture (ISA) of a generic component are presented. Futhermore, two approaches are discussed for altering the flow of execution using mechanisms of subprogram and interrupt. A comprehensive approach is used, with examples drawn from current and past technologies that illustrate theoretical concepts, making them accessible.
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02/2021
1st Edition
ISTE Ltd
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Wiley
€172.10
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Person
Philippe Darche is Maître de conférences in Information Technology at the Institut Universitaire de Technologie (IUT) de Paris and a researcher at LIP6 at Sorbonne University in the Inria DeLyS (DistributEd aLgorithms and sYstemS) team, France. He is the author of five books in the field of computer architecture.
Content
- Cover
- Half-Title Page
- Title Page
- Copyright Page
- Contents
- Quotation
- Preface
- About the book
- Multi-level organization
- Introduction
- 1. Coding and Addressing Modes
- 1.1. Encoding and formatting an instruction
- 1.1.1. Code compression
- 1.2. Addressing modes
- 1.2.1. Immediate addressing
- 1.2.2. Register addressing
- 1.2.3. Memory addressing modes
- 1.2.4. Other addressing modes
- 1.2.5. Summary on addressing
- 1.3. Conclusion
- 2. Instruction Set and Class
- 2.1. Definitions
- 2.2. Transfer instructions
- 2.2.1. Data transfer
- 2.2.2. Address manipulation instructions
- 2.3. Data processing instructions
- 2.3.1. Arithmetic instructions for integers
- 2.3.2. Bit manipulation instructions
- 2.4. Control transfer instructions
- 2.4.1. Branchings
- 2.4.2. Conditional execution
- 2.4.3. Iteration control
- 2.4.4. Subroutine call and return instructions
- 2.5. Environmental instructions
- 2.5.1. Interrupt request and interrupt return instructions13
- 2.5.2. Stopping instructions
- 2.5.3. Processor management
- 2.5.4. Memory management
- 2.5.5. Hardware detection
- 2.5.6. Debugging
- 2.5.7. Updating
- 2.5.8. Verification
- 2.5.9. Various
- 2.6. Parallelism instructions
- 2.6.1. Atomic instructions
- 2.6.2. Synchronization instructions
- 2.7. Extensions to instruction sets
- 2.7.1. Multimedia extension
- 2.7.2. Extension for signal processing
- 2.7.3. Cryptography
- 2.7.4. Randomization management
- 2.7.5. Implications
- 2.8. Various instructions
- 2.8.1. Instructions for handling (strings of) characters
- 2.8.2. Input/output instructions
- 2.8.3. High-level instructions
- 2.8.4. Arithmetic instructions specific to a representation of particular numbers
- 2.8.5. An unusual instruction
- 2.9. Conclusion
- 3. Additional Concepts
- 3.1. Concepts associated with the instruction set and programming
- 3.1.1. llegal, non-implemented, invalid, reserved and trusted instructions
- 3.1.2. Alignment or framing of instructions
- 3.1.3. Orthogonality and symmetry
- 3.1.4. Pure, re-entrant and relocatable codes and code for read-only memory
- 3.1.5. Levels of programming languages
- 3.2. Concepts linked to execution
- 3.2.1. Consequences for execution time and memory requirements
- 3.2.2. Execution modes
- 3.2.3. Portability
- 3.2.4. Virtualization
- 3.3. Hardware and software compatibilities
- 3.3.1. Hardware compatibility
- 3.3.2. Software compatibility
- 3.3.3. Upward and downward compatibilities
- 3.4. Measuring processor performances
- 3.4.1. Clock rate
- 3.4.2. Number of instructions per cycle
- 3.4.3. Execution time
- 3.4.4. Benchmark suites
- 3.4.5. Development of performances over time
- 3.5. Criteria for choosing
- 3.6. Conclusion
- 4. Subroutine
- 4.1. Stack memory
- 4.2. Subroutine
- 4.2.1. Nested calls
- 4.2.2. Execution context
- 4.2.3. Passing parameters and call conventions
- 4.3. Conclusion
- 5. Interrupt Mechanism
- 5.1. Origin, definition and classification
- 5.2. External causes
- 5.2.1. Execution context
- 5.2.2. Sources
- 5.2.3. Masking
- 5.2.4. Consideration and priority
- 5.2.5. Interrupt controller
- 5.3. Nested interrupts
- 5.4. Internal causes
- 5.5. Debugging
- 5.6. Priority between internal and external interrupts
- 5.7. Identification of the source and vectorization
- 5.8. Nested and queued interrupts
- 5.9. Uses
- 5.10. Interrupts and execution modes
- 5.11. Interrupts and advanced architectures
- 5.12. Conclusion
- Conclusion of Volume 4
- Exercises
- Chapter 1. Exercises
- Chapter 2. Exercises
- Chapter 5. Exercises
- Appendix: Tables for Encoding and Decoding Instructions
- Acronyms
- References
- Index
- Other titles from iSTE in Computer Engineering
- EULA
