Microprocessor 2
Description
This first volume focuses more particularly on the first generations of microprocessors, that is to say those that handle integers in 4 and 8-bit formats. The first chapter presents the calculation function and reminds the memory function. The following is devoted to notions of calculation model and architecture. The concept of bus is then presented. Chapters 4 and 5 can then address the internal organization and operation of the microprocessor first in hardware and then software. The mechanism of the function call, conventional and interrupted, is more particularly detailed in a separate chapter. The book ends with a presentation of architectures of the first microcomputers for a historical perspective.
The knowledge is presented in the most exhaustive way possible with examples drawn from current and old technologies that illustrate and make accessible the theoretical concepts. Each chapter ends if necessary with corrected exercises and a bibliography. The list of acronyms used and an index are at the end of the book.
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Content
Quotation ix
Preface xi
Introduction xv
Chapter 1. Basic Definitions 1
1.1. General points regarding communication 1
1.2. Main characteristics 3
1.3. Synchronism and asynchrony 11
1.4. Coding data 21
1.5. Communication protocol 22
1.6. Access arbitration 31
1.7. Conclusion 45
Chapter 2. Transactions and Special Cycles 47
2.1. Transaction 47
2.1.1. Transaction pipeline 47
2.1.2. Splitting the transaction 50
2.2. Special cycles 51
2.2.1. Managing interruption 52
2.2.2. Managing direct memory access 54
2.2.3. Bus Mastering 55
2.2.4. Detection and correction of errors 55
2.2.5. Multiprocessor aspect 55
2.3. Conclusion 56
Chapter 3. Bus Interfaces 57
3.1. Functional modules 57
3.2. Associated signals 59
3.3. Interfacing logic 62
3.3.1. Transmission lines 63
3.3.2. Integrity of the signal 64
3.3.3. Terminating a line 65
3.3.4. Driver and receiver 67
3.3.5. Differential and single-ended links 70
3.3.6. Topologies 72
3.3.7. Electronic technologies 75
3.4. Insertion-withdrawal under tension 76
3.5. Test and debugging 77
3.6. Bus limits 77
3.7. Conclusion 81
Chapter 4. Bus Classifications 83
4.1. Multibus architecture 83
4.1.1. Segmented buses 85
4.1.2. Hierarchical buses 86
4.1.3. Multiple buses 87
4.1.4. Bridge 88
4.2. Classification of digital system buses 91
4.2.1. Local bus 91
4.2.2. Memory buses 93
4.2.3. Link buses 94
4.2.4. Expansion slot bus 96
4.2.5. Expansion buses 101
4.2.6. I/O buses 101
4.2.7. Backplane and centerplane buses 102
4.2.8. Fieldbus 107
4.2.9. SoC: from bus to network 107
4.2.10. Power bus 113
4.3. Summary: bus classifications 119
Conclusion of Volume 2 121
Exercises 123
Acronyms 127
References 145
Index 155
