FinFET/GAA Modeling for IC Simulation and Design

Yogesh Singh Chauhan is a Chair Professor in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, nanosheet/gate-all-around FETs, FDSOI transistors, negative capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices.Chenming Hu is TSMC Distinguished Chair Professor Emeritus at the University of California Berkeley, United States. He was the Chief Technology Officer of TSMC. He received the US Presidential Medal of Technology and Innovation from Pres. Barack Obama for developing the first 3D thin-body transistor FinFET, MOSFET reliability models and leading the development of BSIM industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. He received the highest honor of IEEE, the IEEE Medal of Honor, and its Andrew Grove Award, Solid Circuits Award, and the Nishizawa Medal. He also received the Taiwan Presidential Science Prize and UC Berkeley's highest honor for teaching - the Berkeley Distinguished Teaching Award.Sayeef Salahuddin is the TSMC Distinguished Chair Professor at the University of California, Berkeley He received the Presidential Early Career Award for Scientists and Engineers by President Obama among several other early career awards from multiple federal agencies. He also received the IEEE Andrew S Grove Award for his pioneering work in ferroelectric negative capacitance and its incorporation into the most advanced DRAM memory and back-end capacitors. He is a Fellow of the IEEE, APS and AAAS and is the editor-in-chief of the IEEE Electron Devices Letters.Girish Pahwa is an assistant professor at the International College of Semiconductor Technology at National Yang Ming Chiao Tung University. Girish's research primarily focuses on the modeling, simulation, and device-circuit co-design of upcoming and emerging nanoscale technologies. Before his current role, Girish held multiple positions in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley including assistant professional researcher, postdoctoral scholar, and research and development engineer. He also served as the inaugural executive director of the Berkeley Device Modeling Center (BDMC) and made significant contributions to the BSIM suite of compact models. His notable works include the development of industry-focused compact models for cryogenic CMOS operation, ferroelectric devices, high-voltage MOSFETs, and thin film transistors. Girish has received several prestigious awards, including the IEEE EDS Early Career Award (2022), the Outstanding Ph.D. Thesis Award from IIT Kanpur (2020), and the Best Paper Award at the IEEE International Conference on Emerging Electronics (2016). He is an active member of the IEEE EDS Compact Modeling Committee and the IEEE EDS Electronic Materials Committee. He has served as a reviewer for several journals and conferences and has been part of the technical program committee for the IEEE Electron Devices Technology and Manufacturing (EDTM) conference. Girish earned his Ph.D. and master's degrees in electrical engineering from the Indian Institute of Technology (IIT) Kanpur and his bachelor's degree in electronics and communication engineering from Delhi Technological University.