Substrate Noise Coupling in Analog/RF Circuits

Name: Substrate Noise Coupling in Analog/RF Circuits
Brand: Artech House
Price: 92.49 EUR
Availability: OnlineOnly

Stephane Bronckers(Author)

Artech House (Publisher)

1st Edition

Published on 1. January 2010

270 pages

E-Book

PDF with Adobe-DRM

System requirements

978-1-59693-272-2 (ISBN)

€92.49incl. 7% vat

System requirements

for PDF with Adobe-DRM

E-Book Single Licence

Available for download

Description

More details

Other editions

Content

Substrate Noise Coupling in Analog/RF Circuits
Contents
Foreword
Preface
Acknowledgments
Chapter 1 Introduction
1.1 INTRODUCTION AND MOTIVATION
1.2 BOOK OVERVIEW
References
Chapter 2 Substrate Noise Propagation
2.1 INTRODUCTION
2.2 MODELING THE SUBSTRATE
2.2.1 Analytical Resistance Calculation Between Two Contacts
2.2.2 Finite Difference Method
2.2.3 Finite Element Method
2.3 THE SUBSTRATE MODELED WITH FDM
2.3.1 Experimental Description
2.3.2 Analysis of the Substrate Noise Propagation
2.3.3 Conclusions
2.4 THE SUBSTRATE AS A FINITE ELEMENT MODEL
2.4.1 Simulation Methodology
2.4.2 Dealing with N-Doped Regions
2.4.3 Simulation Setup for the Test Structure
2.4.4 Comparison
2.4.5 Conclusions
2.5 CONCLUSIONS
References
Chapter 3 Passive Isolation Structures
3.1 INTRODUCTION
3.2 OVERVIEW AND DESCRIPTION OF THE DIFFERENT TYPES OFPASSIVE ISOLATION STRUCTURES
3.2.1 The Template Layout
3.2.2 Integrating the Different Types of Guard Rings
3.2.3 Simulation Setup
3.3 PREDICTION AND UNDERSTANDING OF GUARD RINGS
3.3.1 Reference Structure
3.3.2 P-Well Block Isolation
3.3.3 N-Well Isolation
3.3.4 P+ Guard Ring Shielding
3.3.5 Triple Well Shielding
3.3.6 Comparison and Conclusion
3.4 DESIGN OF AN EFFICIENT P+ GUARD RING
3.4.1 Impedance of the Ground Interconnect
3.4.2 Width of the P+ Guard Ring
3.4.3 Distance to the Victim
3.4.4 Guidelines for Good P+ Guard Ring Design
3.5 CONCLUSIONS
References
Chapter 4 Noise Coupling in Active Devices
4.1 INTRODUCTION
4.2 SUBSTRATE NOISE IMPACT ON ANALOG DESIGN
4.3 IMPACT SIMULATION METHODOLOGY
4.3.1 EM Simulation
4.3.2 Circuit Simulation
4.4 TRANSISTOR TEST BENCH
4.4.1 Description of the Transistor Under Test
4.4.2 Modeling the Transistor Test Bench
4.4.3 Experimental Validation
4.5 SUBSTRATE NOISE COUPLING MECHANISMS IN A TRANSISTOR
4.5.1 Analyzing the Different Coupling Mechanisms in a Transistor
4.5.2 Description and Measurement of the Device Under Test
4.5.3 Modeling Different Substrate Noise Coupling Mechanisms
4.5.4 Quantifying the Different Substrate Noise Coupling Mechanisms
4.5.5 Experimental Validation of the Substrate Noise Coupling Mechanisms
4.6 CONCLUSIONS
References
Chapter 5 Measuring the Coupling Mechanisms in Analog/RF Circuits
5.1 INTRODUCTION
5.2 MEASUREMENT-BASED IDENTIFICATION OF THE DOMINANTSUBSTRATE NOISE COUPLING MECHANISMS
5.2.1 Measurement of the Different Spurs
5.2.2 Sensitivity Functions
5.2.3 Determining the Influence of the PCB
5.3 EXAMPLE: 900 MHZ LC-VCO
5.3.1 Description of the LC-VCO
5.3.2 Substrate Sensitivity Measurements
5.3.3 Revealing the Dominant Coupling Mechanism for FM Spurs
5.3.4 Revealing the Dominant Coupling Mechanism for AM Spurs
5.3.5 Influence of the PCB Decoupling Capacitors on the Substrate NoiseImpact
5.3.6 Conclusions
5.4 STUDY OF THE COUPLING MECHANISMS BETWEEN A POWER AMPLIFIER AND AN LC-VCO
5.4.1 Description of the Design of the PPA and the LC-VCO
5.4.2 Coupling Mechanisms Between the PPA and the LC-VCO
5.4.3 Measuring the Dominant Coupling Mechanisms
5.4.4 Conclusions
5.5 CONCLUSIONS
References
Chapter 6 The Prediction of the Impact of Substrate Noise on Analog/RF Circuits
6.1 INTRODUCTION
6.2 THE SUBSTRATE MODELED WITH FDM
6.2.1 Impact Simulation Methodology
6.2.2 Prediction of the Impact of Substrate Noise from DC Up to LO Frequency
6.2.3 Experimental Validation of the Simulation Methodology
6.2.4 Conclusions
6.3 SUBSTRATE MODELED BY THE FEM METHOD
6.3.1 Impact Simulation Methodology
6.3.2 Prediction of the Impact of Substrate Noise
6.3.3 Verification with Measurements
6.3.4 Conclusions
6.4 TECHNIQUES TO REDUCE SUBSTRATE NOISE COUPLING
6.4.1 Layout Techniques to Reduce the Substrate Noise Coupling
6.4.2 Circuit Techniques to Reduce the Substrate Noise Coupling
6.4.3 3D Stacking as a Solution to Substrate Noise Issues
6.4.4 Separated Analog/Digital Ground
6.4.5 Shared Analog/Digital Ground
6.4.6 Experimental Validation
6.4.7 Conclusions
6.5 CONCLUSIONS
References
Chapter 7 Noise Coupling in Analog/RF Systems
7.1 INTRODUCTION
7.2 IMPACT SIMULATION METHODOLOGY
7.2.1 EM Simulation
7.2.2 Parasitic Extraction
7.2.3 Circuit Simulation
7.3 ANALYZING THE IMPACT OF SUBSTRATE NOISE IN ANALOG/RFSYSTEMS
7.3.1 Analysis of the Propagation of Substrate Noise
7.3.2 Analyzing the Substrate Noise Coupling
7.4 SUBSTRATE NOISE IMPACT ON A 48-53 GHZ LC-VCO
7.4.1 Description of the LC-VCO
7.4.2 Simulation Setup
7.4.3 Conclusion
7.5 IMPACT OF SUBSTRATE NOISE ON A DC TO 5 GHZ WIDEBAND RECEIVER
7.5.1 Description of the Wideband Receiver
7.5.2 Simulation Setup
7.5.3 Parasitic Extraction
7.5.4 Circuit Simulation
7.5.5 Revealing the Dominant Coupling Mechanism
7.5.6 Experimental Verification
7.6 CONCLUSIONS AND DISCUSSION
7.6.1 Conclusions
7.6.2 Discussion
References
Appendix A Narrowband Frequency Modulation of LC Tank VCOs
References
Appendix B Port Conditions
References
List of Acronyms
About the Authors
Index
Color insert

System requirements

Save as PDF Copy link into clipboard

Schweitzer Fachinformationen

Substrate Noise Coupling in Analog/RF Circuits

Description

More details

Other editions

Additional editions

Content

System requirements