VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms

Name: VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms | 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers
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26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers

Nicola Bombieri Graziano Pravadelli Masahiro Fujita Todd Austin Ricardo Reis(Editor)

Springer (Publisher)

Published on 25. June 2019

XIV, 281 pages

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978-3-030-23425-6 (ISBN)

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Content

Intro
Preface
Organization
Contents
A 65nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load
1 Introduction
2 Proposed Synthesizable LDO
2.1 Architecture
2.2 Transfer Function of the Control Loop
2.3 Design Procedure of the Proposed LDO
3 Prototype Implementation and Measurement Results
4 Conclusion
References
An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication
1 Introduction
2 Pulsed-Signaling Techniques
3 Pulsed-Index Communication Interface Architecture (PICIA)
3.1 Register Set
3.2 Instruction Formats
3.3 Addressing Modes
3.4 Interrupts
3.5 External I/O
4 PICIA Assembly Language
4.1 Type 1 Instructions (I-Type 1)
4.2 Type 2 Instructions (I-Type 2)
4.3 Type 3 Instructions (I-Type 3)
5 Experimental Verification and Results
6 Securing PICIA
6.1 Extended Register Set
6.2 Extended Instruction Set
6.3 Instruction Format
7 Conclusions
References
The Connection Layout in a Lattice of Four-Terminal Switches
1 Introduction
2 Rearranging the Lattice
2.1 Solving Problem1
2.2 Hardness of Problem1
2.3 Solving Problem2
2.4 Hardness of Problem2
3 Solving Problem3
3.1 Impossible Instances
3.2 Hardness of Problem3
3.3 Heuristics for Problem3
4 Experimental Results
5 Concluding Remarks
References
Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS
1 Introduction
2 Parallel Memories: Challenges and Solutions
2.1 Parallel Memories
2.2 The Polymorphic Register File and PolyMem
2.3 Matrix Storage in a Parallel Memory
3 Implementation Details
4 Evaluation and Results
4.1 Experimental Setup
4.2 Results
5 Application Case-Studies
5.1 Matrix Multiplication (MM)
5.2 Markov Chain and the Matrix Power Operation
6 Related Work
7 Conclusion and Future Work
References
Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields
1 Introduction
1.1 Problem Description, Objectives, and Contributions
2 Review of Previous Work
3 Preliminaries: Notation and Background Results
4 Algebraic Miter for Equivalence Checking
5 Formulating the Rectification Check
5.1 Single Fix Rectification
6 Craig Interpolants in Finite Fields
6.1 Computing a Rectification Function from Craig Interpolants
7 Efficient Gröbner Basis Computations for EL and EH
8 Experimental Results
9 Conclusion
References
Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis
1 Introduction
2 Related Works
2.1 Adaptive ConvNets
2.2 Fixed-Point Quantization
3 Energy-Accuracy Scalable Convolution
3.1 SW: Multiprecision Convolution
3.2 HW: Variable-Latency Processing Element
3.3 Hardware Characterization
4 Energy-Driven Precision Assignment
4.1 Fixed-Point Quantization
4.2 Multiprecision Fixed-Point ConvNets
5 Results
5.1 Experimental Set-up
5.2 Benchmarks
5.3 Results
6 Conclusions
References
ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code
1 Introduction
2 Preliminaries
2.1 Galois Field Arithmetic
2.2 Basics of BCH Encoding and Decoding Operation
2.3 In-Memory Computing Using ReRAM
3 Methodology
3.1 Generation of GF Elements
3.2 Encoding and Decoding Operations
4 Experiment
5 Conclusion
References
Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems
1 Introduction
2 Background and Related Work
2.1 Memristor
2.2 Memristor Aided LoGIC (MAGIC)
2.3 In-Memory Computation Using Memristor Crossbar
2.4 Fanout
3 Proposed Approach
3.1 Overall Approach: Case 1
3.2 Mapping Scenario Analysis: Case 1
3.3 Overall Approach: Case 2
3.4 Mapping Scenario Analysis: Case 2
4 Experimental Results
4.1 Experimental Setup
4.2 Results and Analysis
5 Conclusions
References
Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis
1 Introduction
2 Background
2.1 Target Application: Neural Network Simulation
2.2 Target Architecture: Neuromorphic MPSoCs Board
3 Problem Formulation
3.1 Problem Relaxation
3.2 Graph Partitioning
4 Placement
4.1 Naïve Placement
4.2 Spectral Embedding
4.3 Scotch
4.4 Simulated Annealing
5 Results
6 Conclusions
References
Improved Test Solutions for COTS-Based Systems in Space Applications
Abstract
1 Introduction
2 The MaMMoTH-Up System
2.1 General Architecture and Functions
2.2 The OR1200 Processor
2.3 The UART Core
3 Comparing the Functional and the Structural Approaches
3.1 Background
3.2 The Functional Test
3.3 The Structural Test
3.4 Results
4 Safe Faults
4.1 Safe Faults Identification
4.2 Results
5 Conclusions
Acknowledgments
References
Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection
1 Introduction
2 Memories Based on STT-MRAM
3 Read and Write Operations of STT-MRAM Cells
3.1 Read Operation
3.2 Write Operation
4 Write Time Definition for an STT-MRAM Cell
5 Analysis of STT-MRAM Behavior Under Short Defects
5.1 Defect Model for Short Defects in the STT-MRAM
5.2 Impact of Short Defects on Write Operation
5.3 Impact of Short Defects on the Read Operation
5.4 Summary Behavior of Write and Read Operation Under Short Defects
6 Proposed Test Technique
6.1 Fundamental of the Proposed Test Technique
6.2 Proposed Test Circuitry
7 Cost and Comparison of Our Proposal with Logic Test
7.1 Detection Probability Comparison
7.2 Hardware Comparison
7.3 Other Issues
7.4 Short Defects that Can Be Detected
8 Conclusions
References
Assessment of Low-Budget Targeted Cyberattacks Against Power Systems
1 Introduction
2 Background
2.1 Power Systems
2.2 Protection and Control Equipment
2.3 Grid Modernization
2.4 Global Positioning System
3 Open Sourcing Power System Cyberattacks
3.1 Threat Model
3.2 Open Source Intelligence for Modeling Power Systems
3.3 Identifying Critical Locations with Contingency Analysis
3.4 Open Source Exploitation - OSEXP
3.5 Instantiation of an OSEXP Attack: GPS Time Spoofing Against PMUs
4 Experimental Evaluation
4.1 Power System Modeling
4.2 GPS Experimental Setup
4.3 Budget
5 Conclusions
References
Efficient Hardware/Software Co-design for NTRU
1 Introduction
2 Related Works
3 NTRU
3.1 Notation
3.2 Short Vector Encryption Scheme (SVES)
3.3 NTRU with SVES
4 NTRU Full Hardware Architecture
4.1 Convolution (CONV)
4.2 Blinding Polynomial Generation Method (BPGM)
4.3 Mask Generation Function (MGF)
4.4 Modulo Reduction (MOD P)
5 NTRU HW/SW Co-design
5.1 Software Implementation
6 Security Analysis
6.1 Optimized Architecture
6.2 Vulnerabilities
7 Results
7.1 Results of Full Hardware Implementation
7.2 Results of HW/SW Co-design
8 Conclusion
References
Correction to: Improved Test Solutions for COTS-Based Systems in Space Applications
Correction to: Chapter "Improved Test Solutions for COTS-Based Systems in Space Applications" in: N. Bombieri et al. (Eds.): VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, IFIP AICT 561, https://doi.org/10.1007/978-3-030-23425-6_10
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VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms

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