Advanced MOS Devices and their Circuit Applications
1st Edition
Published on 8. January 2024
160 pages
978-1-003-83112-9 (ISBN)
Description
This text comprehensively discusses the advanced MOS devices and their circuit applications with reliability concerns. Further, an energy-efficient Tunnel FET-based circuit application will be investigated in terms of the output voltage, power efficiency, energy consumption, and performances using the device circuit co-design approach.
The book:
Discusses advanced MOS devices and their circuit design for energy- efficient systems on chips (SoCs)
Covers MOS devices, materials, and related semiconductor transistor technologies for the next-generation ultra-low-power applications
Examines the use of field-effect transistors for biosensing circuit applications and covers reliability design considerations and compact modeling of advanced low-power MOS transistors
Includes research problem statements with specifications and commercially available industry data in the appendix
Presents Verilog-A model-based simulations for circuit analysis
The volume provides detailed discussions of DC and analog/RF characteristics, effects of trap-assisted tunneling (TAT) for reliability analysis, spacer-underlap engineering methodology, doping profile analysis, and work-function techniques. It further covers novel MOS devices including FinFET, Graphene field-effect transistor, Tunnel FETS, and Flash memory devices. It will serve as an ideal design book for senior undergraduate students, graduate students, and academic researchers in the fields including electrical engineering, electronics and communication engineering, computer engineering, materials science, nanoscience, and nanotechnology.
The book:
Discusses advanced MOS devices and their circuit design for energy- efficient systems on chips (SoCs)
Covers MOS devices, materials, and related semiconductor transistor technologies for the next-generation ultra-low-power applications
Examines the use of field-effect transistors for biosensing circuit applications and covers reliability design considerations and compact modeling of advanced low-power MOS transistors
Includes research problem statements with specifications and commercially available industry data in the appendix
Presents Verilog-A model-based simulations for circuit analysis
The volume provides detailed discussions of DC and analog/RF characteristics, effects of trap-assisted tunneling (TAT) for reliability analysis, spacer-underlap engineering methodology, doping profile analysis, and work-function techniques. It further covers novel MOS devices including FinFET, Graphene field-effect transistor, Tunnel FETS, and Flash memory devices. It will serve as an ideal design book for senior undergraduate students, graduate students, and academic researchers in the fields including electrical engineering, electronics and communication engineering, computer engineering, materials science, nanoscience, and nanotechnology.
More details
Edition
1. Auflage
Language
English
Place of publication
London
United Kingdom
Publishing group
Taylor & Francis Ebooks
Target group
College/higher education
Illustrations
25 Tables, black and white; 84 Line drawings, black and white; 25 Halftones, black and white; 72 Illustrations, color; 37 Illustrations, black and white
ISBN-13
978-1-003-83112-9 (9781003831129)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
Ankur Beohar | Ribu Mathew | Abhishek Kumar Upadhyay
Advanced MOS Devices and their Circuit Applications
Book
09/2025
1st Edition
CRC Press
€72.90
Shipment within 10-20 days
Ankur Beohar | Ribu Mathew | Abhishek Kumar Upadhyay
Advanced MOS Devices and their Circuit Applications
Book
01/2024
1st Edition
CRC Press
€126.50
Shipment within 10-20 days
Persons
Dr. Ankur Beohar (Senior member IEEE) obtaineda PhD degree in electrical engineering from the Indian Institute of Technology (IIT), Indore, MP, India, in 2018. After getting his PhD, he worked as a postdoctoral fellow in the Device Modeling Group, IISER, Bhopal, and then as a research scientist for one year under awarded Scientist Pool scheme of Council of Scientific and Industrial Research (CSIR), New Delhi. Currently, he is working as an assistant professor at Vellore Institute of Technology (VIT) Bhopal. He is an IEEE Senior Member and a Secretary of IEEE, Circuit and System Society, MP section, India. He completed his M.Tech degree in VLSI and Embedded System Design from MANIT Bhopal and B.Tech (Electronics) from RGPV University Bhopal in 2010 and 2005. He has a research and academic work experience of more than 13 years. He has a renowned research experience in the field of low-power device circuit design Memory Circuit Design and Reliability. His current research is related to new-generation innovative devices, such as optimization of gate all around (GAA)-Tunnel field effect transistor (TFET) with spacer engineering and its circuit applications. Currently, he is working in the research project sanctioned by the Science and Engineering Research Board (SERB) under the Teachers Associateship Research Excellence (TARE) scheme. Dr. Beohar has published more than 35 research publications in various peer- reviewed international conferences and SCI journals. Along with this, he has reviewed more than 100+ journal and conferences articles.
Dr. Abhishek Kumar Upadhyay obtained a PhD in electrical engineering from the Indian Institute of Technology (IIT), Indore, MP, India, in 2019. After getting his PhD, he worked for one year as a postdoctoral fellow in the Model Group, Material to System Integration Laboratory, University of Bordeaux, France, and then as a staff scientist in the Chair of Electronics Devices and Integrated Circuits at Technische Universitaet Dresden, Germany, for two years. Currently he is working as an R&D rngineer in X-FAB GmbH, Dresden, Germany. He is the author of several research articles.
Dr. Ribu Mathew holds a doctorate degree in electronics engineering from Vellore Institute of Technology (VIT) University, Chennai Campus. A gold medallist in his post graduation, Dr. Mathew completed his MTech in VLSI design and BTech in electronics and communication engineering. In his doctoral research work, he has contributed in the field of design, modelling, and fabrication of NEMS technology piezoresistive readout-based nano cantilever sensors for chemical and biological sensing applications. In addition to the compu- tational knowledge in industrial standard NEMS devices, he has gained experience in NEMS/IC layout tools and clean room fabrication technologies from CeNSE, IISc Bangalore. He has published several research papers in reputed international journals and conferences. His research areas include the design, modelling, and fabrication of MEMS/NEMS technology- based sensor and actuator systems, especially micro/nano cantilever and diaphragm-based devices, bio-MEMS, analog/RF IC design, SoC design, and device modeling. Currently he is working as an Associate Professor, MAHE, MANIPAL University, Karnataka.
Professor Santosh Kumar Vishvakarma received the BSc in electronics from the University of Gorakhpur, Gorakhpur, in 1999, the MSc in electronics from Devi Ahilya Vishwavidyalaya, Indore, India, in 2001, the MTech in microelectronics from Punjab University, Chandigarh, India, in 2003, and the PhD in microelectronics and VLSI from the Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, India, in 2010. From 2009 to 2010, he was with University Graduate Center, Kjeller, Norway, as a postdoctoral fellow under European Union COMON project. Professor Vishvakarma is with the Department of Electrical Engineering, Indian Institute of Technology Indore, MP, India as a professor at IIT Indore. He is leading the Nanoscale Devices and VLSI Circuit and System Design (NSDCS) Laboratory since 2010. He is engaged with teaching and research in the areas of:
Energy-efficient and reliable SRAM memory design
Enhancing performance and configurable architecture for DNN accelerators
SRAM based in-memory computing architecture for edge AI
Reliable, secure design for IoT applications
Design for reliability
He has supervised a total of seventeen PhD students, and currently six students are working with his group. He has authored or co-authored more than 175 research papers in peer-reviewed international journals and conferences. He was also granted 04 Indian Patent from IIT Indore and has thirteen sponsored research projects. He is a senior member of IEEE, professional member of VLSI Society of India, associate member of Institute of Nanotechnology, and life member of Indian Microelectronics Society (IMS), India.
Dr. Abhishek Kumar Upadhyay obtained a PhD in electrical engineering from the Indian Institute of Technology (IIT), Indore, MP, India, in 2019. After getting his PhD, he worked for one year as a postdoctoral fellow in the Model Group, Material to System Integration Laboratory, University of Bordeaux, France, and then as a staff scientist in the Chair of Electronics Devices and Integrated Circuits at Technische Universitaet Dresden, Germany, for two years. Currently he is working as an R&D rngineer in X-FAB GmbH, Dresden, Germany. He is the author of several research articles.
Dr. Ribu Mathew holds a doctorate degree in electronics engineering from Vellore Institute of Technology (VIT) University, Chennai Campus. A gold medallist in his post graduation, Dr. Mathew completed his MTech in VLSI design and BTech in electronics and communication engineering. In his doctoral research work, he has contributed in the field of design, modelling, and fabrication of NEMS technology piezoresistive readout-based nano cantilever sensors for chemical and biological sensing applications. In addition to the compu- tational knowledge in industrial standard NEMS devices, he has gained experience in NEMS/IC layout tools and clean room fabrication technologies from CeNSE, IISc Bangalore. He has published several research papers in reputed international journals and conferences. His research areas include the design, modelling, and fabrication of MEMS/NEMS technology- based sensor and actuator systems, especially micro/nano cantilever and diaphragm-based devices, bio-MEMS, analog/RF IC design, SoC design, and device modeling. Currently he is working as an Associate Professor, MAHE, MANIPAL University, Karnataka.
Professor Santosh Kumar Vishvakarma received the BSc in electronics from the University of Gorakhpur, Gorakhpur, in 1999, the MSc in electronics from Devi Ahilya Vishwavidyalaya, Indore, India, in 2001, the MTech in microelectronics from Punjab University, Chandigarh, India, in 2003, and the PhD in microelectronics and VLSI from the Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, India, in 2010. From 2009 to 2010, he was with University Graduate Center, Kjeller, Norway, as a postdoctoral fellow under European Union COMON project. Professor Vishvakarma is with the Department of Electrical Engineering, Indian Institute of Technology Indore, MP, India as a professor at IIT Indore. He is leading the Nanoscale Devices and VLSI Circuit and System Design (NSDCS) Laboratory since 2010. He is engaged with teaching and research in the areas of:
Energy-efficient and reliable SRAM memory design
Enhancing performance and configurable architecture for DNN accelerators
SRAM based in-memory computing architecture for edge AI
Reliable, secure design for IoT applications
Design for reliability
He has supervised a total of seventeen PhD students, and currently six students are working with his group. He has authored or co-authored more than 175 research papers in peer-reviewed international journals and conferences. He was also granted 04 Indian Patent from IIT Indore and has thirteen sponsored research projects. He is a senior member of IEEE, professional member of VLSI Society of India, associate member of Institute of Nanotechnology, and life member of Indian Microelectronics Society (IMS), India.
Content
Chapter 1
An Overview of DC/RF Performance of Nanosheet Field Effect Transistor for Future Low Power Applications
Arun A V, Sajeesh M, Jobymol Jacob, J Ajayan
Chapter 2
Device Design and Analysis of 3D SCwRD Cylindrical (Cyl) Gate-All-Around (GAA) Tunnel FET using Split-Channel and spacer Engineering
Ankur Beohar, Seema Tiwari, Kavita Khare, Santosh Kumar Vishvakarma
Chapter 3
Investigation of High-K Dielectrics for Single and Multi-Gate FETs
Sresta Valasa, Shubham Tayal, Laxman Raju Thoutam
Chapter 4
Measurement of Back Gate Biasing For Ultra Low Power Subthreshold Logic in FinFET Device
Ajay Kumar Dadoria, Uday Panwar, Narendra Kumar Garg
Chapter 5
Compact Analytical Model for Graphene Field Effect Transistor: Drift-Diffusion Approac
Abhishek Kumar Upadhyay1, Siromani Balmukund Rahi, Billel
Chapter 6
Design of CNTFET-Based Ternary Logic Flip-Flop and Counter Circuits using Unary Operators
Trapti Sharma
Chapter 7
NOVEL RADIATION HARDENED LOW POWER 12 TRANSISTORS SRAM CELL FOR AEROSPACE APPLICATION
Vancha sharath reddy, Arjun singh yadav, Soumya sengupta
Chapter 8
Nanoscale CMOS Static Random Access Memory (SRAM) Design: Trends and Challenges
Sunanda Ambulkar, Jeetendra Kumar Mishra
Chapter 9
Variants based Gate Modification (VGM) technique for reducing leakage power and short channel effect in DSM circuits
Uday Panwar, Ajay Kumar Dadoria
Chapter 10
A Novel Approach for High Speed and low Power by using Nano-VLSI Interconnects
Narendra Kumar Garg , Vivek Singh Kushwah, Ajay Kumar Dadoria
An Overview of DC/RF Performance of Nanosheet Field Effect Transistor for Future Low Power Applications
Arun A V, Sajeesh M, Jobymol Jacob, J Ajayan
Chapter 2
Device Design and Analysis of 3D SCwRD Cylindrical (Cyl) Gate-All-Around (GAA) Tunnel FET using Split-Channel and spacer Engineering
Ankur Beohar, Seema Tiwari, Kavita Khare, Santosh Kumar Vishvakarma
Chapter 3
Investigation of High-K Dielectrics for Single and Multi-Gate FETs
Sresta Valasa, Shubham Tayal, Laxman Raju Thoutam
Chapter 4
Measurement of Back Gate Biasing For Ultra Low Power Subthreshold Logic in FinFET Device
Ajay Kumar Dadoria, Uday Panwar, Narendra Kumar Garg
Chapter 5
Compact Analytical Model for Graphene Field Effect Transistor: Drift-Diffusion Approac
Abhishek Kumar Upadhyay1, Siromani Balmukund Rahi, Billel
Chapter 6
Design of CNTFET-Based Ternary Logic Flip-Flop and Counter Circuits using Unary Operators
Trapti Sharma
Chapter 7
NOVEL RADIATION HARDENED LOW POWER 12 TRANSISTORS SRAM CELL FOR AEROSPACE APPLICATION
Vancha sharath reddy, Arjun singh yadav, Soumya sengupta
Chapter 8
Nanoscale CMOS Static Random Access Memory (SRAM) Design: Trends and Challenges
Sunanda Ambulkar, Jeetendra Kumar Mishra
Chapter 9
Variants based Gate Modification (VGM) technique for reducing leakage power and short channel effect in DSM circuits
Uday Panwar, Ajay Kumar Dadoria
Chapter 10
A Novel Approach for High Speed and low Power by using Nano-VLSI Interconnects
Narendra Kumar Garg , Vivek Singh Kushwah, Ajay Kumar Dadoria
