
VLSI-SoC: Technologies for Systems Integration
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Content
- Title
- Preface
- Organization
- Table of Contents
- Emerging Technologies and Nanoscale Computing Fabrics
- Introduction
- Carbon-Based Nanofabrics
- Clusters of Cell-Matrices Architecture
- Fixed Intra-matrix Interconnect Topology Strategy
- Matrix Programming
- Functional Description
- Mapping Example
- Evaluation Methodology
- Cluster Programming
- Model Description
- Experimental Results
- Insights and Future Challenges
- References
- Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS
- Introduction
- Related Work
- The "More Moore" Brick-Walls
- Grand Challenges for Systems-on-Chips Integration
- Heterogeneous Hardware Integration
- Nano-power Computing for Autonomic Systems
- Design and Architectural Complexity
- Simple IP Objects - Sense-Compute-Communicate
- Electronic Design Automation Tools
- Impacts on the Global Hardware Industry
- Conclusions
- References
- Thermal Modeling and Management of Liquid-Cooled 3D Stacked Architectures
- Introduction
- Related Work
- Thermal Modeling and Management
- Design, Modeling, and Management of 3D Systems
- Modeling Framework for Liquid-Cooled 3D Systems
- Grid-Level Thermal Model for 3D Systems with Liquid Cooling
- Modeling the Pump and Liquid Flow Rate
- Joint Flow Rate Control and Job Scheduling
- Temperature Monitoring and Forecasting
- Liquid Flow Rate Control
- Job Scheduling
- Experimental Results
- Conclusion
- References
- Performance and Energy Evaluation of Memory Organizations in NoC-Based MPSoCs under Latency and Task Migration
- Introduction
- Related Work
- The SIMPLE Virtual Platform
- Experimental Setup
- Experiments without Synthetic Traffic
- Performance
- Energy Consumption
- Experiments with Synthetic Traffic
- Performance
- Energy Consumption
- Experiments with Task Migration
- Performance Results
- Energy Consumption Results
- Conclusions and Future Work
- References
- Crosstalk Fault Tolerant NoC: Design and Evaluation
- Introduction
- Related Work
- Crosstalk Fault Tolerant NoC Architectures
- NoC with Link CRC
- NoC With Source CRC
- NoC Hamming on Links
- Fault Modeling and Fault Injection
- Croasstalk Effects
- Maximal Agressor Fault (MAF) Model
- Saboteur Module
- Results
- Area Overhead
- Latency Impact
- Residual Fault Analysis
- Power Consuption
- Conclusions and Future Work
- References
- From Assertion-Based Verification to Assertion-Based Synthesis
- Introduction
- State of the Art
- Assertion-Based Verification
- Automatic Synthesis from Specifications
- Assertion-Based Verification
- Monitors
- Generators
- From Assertion-Based Verification to Assertion-Based Synthesis
- Example: The CDT Design
- Annotations of PSL Properties
- Consistency of the Specification
- Assertion-Based Synthesis
- The Extended-Generator
- Building the Final Design
- Verification of the Approach
- Case Study: Wishbone Crossbar Controller
- A Crossbar Bus and the Wishbone Specification
- Assertion-Based Verification with Horus
- Assertion-Based Synthesis with SyntHorus
- Conclusion
- References
- Power Macro-Modeling Using an Iterative LS-SVM Method
- Introduction
- Related Work
- Power Macro-Modeling
- LS-SVMs
- Kernel Tuning
- Parameter C
- Parameter
- Number of Support Vectors
- Model Optimization
- Weighted Norm
- Iterative Process
- Implementation
- Input Space Analysis
- Computing the Input Weights
- Model Size
- Model Pruning
- Results
- Conclusions
- References
- Enhancing Electromagnetic Attacks Using Spectral Coherence Based Cartography
- Introduction
- DEMA Overview and Improvements
- DEMA Overview
- A Standard DEMA Example
- Improvements of DEMA
- Global Magnitude Squared Incoherence
- Problem Definition
- Fundamentals of Global Magnitude Squared Incoherence
- Coupling WGMSI Criterion with EM near Field Scanning
- Experimental Results
- Experimental Setup
- Analyzed Design
- WGMSI Maps vs. Design Floorplans
- WGMSI and DEMA Attacks
- WGMSI vs. EM Analysis Maps
- Conclusion
- References
- A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures
- Introduction
- Interconnect Modeling Challenges
- Multistep Extrapolated S-Parameter Model
- Parameter Extraction Framework
- Multistep Extrapolation Method
- Extraction of the Initial Parameter Set
- Incremental Extrapolation
- Passivity Enforcement
- Experimental Validation
- Conclusions
- References
- Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis
- Introduction
- Context Adaptive Binary Arithmetic Codec Overview
- CABAD Algorithm Overview
- Related Work
- Bitstream Flow Analysis for Decoder Process
- Design Architecture
- Experimental Results
- Validation Process
- Conclusions and Future Work
- References
- Author Index
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