
Multi-Processor System-on-Chip 2
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complex applications. These applications put huge pressure on memory,
communication devices and computing units. This book, presented in
two volumes Architectures and Applications therefore celebrates the
20th anniversary of MPSoC, an interdisciplinary forum that focuses on
multi-core and multi-processor hardware and software systems. It is this
interdisciplinarity which has led to MPSoC bringing together experts in
these fields from around the world, over the last two decades.
Multi-Processor System-on-Chip 2 covers application-specific MPSoC
design, including compilers and architecture exploration. This second
volume describes optimization methods, tools to optimize and port
specific applications on MPSoC architectures. Details on compilation,
power consumption and wireless communication are also presented, as
well as examples of modeling frameworks and CAD tools. Explanations
of specific platforms for automotive and real-time computing are also
included.
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Persons
Alpes in France. She received her PhD in Computer Science,
Telecommunications and Electronics from Universite Pierre et Marie
Curie in 2016. Her research interests include system-level
modeling/validation of systems-on-chips, and the acceleration of
heterogeneous systems simulation.
Frederic Rousseau is Full Professor at TIMA Lab, Universite Grenoble
Alpes in France. His research interests concern Multi-Processor
Systems-on-Chip design and architecture, prototyping of
hardware/software systems including reconfigurable systems and highlevel synthesis for embedded systems.
Content
- Cover
- Half-Title Page
- Dedication
- Title Page
- Copyright Page
- Contents
- Foreword
- Acknowledgments
- PART 1: MPSoC for Telecom
- 1 From Challenges to Hardware Requirements for Wireless Communications Reaching 6G
- 1.1. Introduction
- 1.2. Breadth of workloads
- 1.2.1. Vision, trends and applications
- 1.2.2. Standard specifications
- 1.2.3. Outcome of workloads
- 1.3. GFDM algorithm breakdown
- 1.3.1. Equation
- 1.3.2. Dataflow processing graph and matrix representation
- 1.3.3. Pseudo-code
- 1.4. Algorithm precision requirements and considerations
- 1.5. Implementation
- 1.5.1. Implementation considerations
- 1.5.2. Design space exploration
- 1.5.3. Measurements for low-end and high-end use cases
- 1.6. Conclusion
- 1.7. Acknowledgments
- 1.8. References
- 2 Towards Tbit/s Wireless Communication Baseband Processing: When Shannon meets Moore
- 2.1. Introduction
- 2.2. Role of microelectronics
- 2.3. Towards 1 Tbit/s throughput decoders
- 2.3.1. Turbo decoder
- 2.3.2. LDPC decoder
- 2.3.3. Polar decoder
- 2.4. Conclusion
- 2.5. Acknowledgments
- 2.6. References
- PART 2: Application-specific MPSoC Architectures
- 3 Automation for Industry 4.0 by using Secure LoRaWAN Edge Gateways
- 3.1. Introduction
- 3.2. Security in IIoT
- 3.3. LoRaWAN security in IIoT
- 3.4. Threat model
- 3.4.1. LoRaWAN attack model
- 3.4.2. IIoT node attack model
- 3.5. Trusted boot chain with STM32MP1
- 3.5.1. Trust base of node
- 3.5.2. Trusted firmware in STM32MP1
- 3.5.3. Trusted execution environments and OP-TEE
- 3.5.4. OP-TEE scheduling considerations
- 3.5.5. OP-TEE memory management
- 3.5.6. OP-TEE client API
- 3.5.7. TEE internal core API
- 3.5.8. Root and chain of trust
- 3.5.9. Hardware unique key
- 3.5.10. Secure clock
- 3.5.11. Cryptographic operations
- 3.6. LoRaWAN gateway with STM32MP1
- 3.7. Discussion and future scope
- 3.8. Acknowledgments
- 3.9. References
- 4 Accelerating Virtualized Distributed NVMe Storage in Hardware
- 4.1. Introduction
- 4.1.1. Virtualization and traditional hypervisors
- 4.1.2. Hyperconverged versus disaggregated cloud architectures
- 4.1.3. NVMe flash storage
- 4.2. Motivation: NVMe storage for the cloud
- 4.2.1. Motivation for a new hypervisor
- 4.2.2. Motivation for accelerating disaggregated storage
- 4.3. Design
- 4.3.1. Optimizing the hypervisor I/O operations
- 4.3.2. Design of accelerated disaggregated storage
- 4.4. Implementation
- 4.4.1. The NexVisor platform
- 4.4.2. Accelerated disaggregated storage
- 4.5. Results
- 4.5.1. Sequential reads
- 4.5.2. Sequential writes
- 4.5.3. Sequential reads on one NVMe drive
- 4.5.4. Network performance
- 4.6. Conclusion
- 4.7. References
- 5 Modular and Open Platform for Future Automotive Computing Environment
- 5.1. Introduction
- 5.2. Outline of this approach
- 5.2.1. Centralized computation, distributed data
- 5.2.2. Modularity and heterogeneity
- 5.2.3. Tools for specification, configuration and integration
- 5.3. Results
- 5.3.1. Hardware platform
- 5.3.2. FACE SW architecture
- 5.3.3. FACE Tool Suite
- 5.4. Use case
- 5.4.1. Adaptive braking system
- 5.5. Conclusion
- 5.6. References
- 6 Post-Moore Datacenter Server Architecture
- 6.1. Introduction
- 6.2. Background: today's blades are from the desktops of the 1980s
- 6.3. Memory-centric server design
- 6.4. Data management accelerators
- 6.5. Integrated network controllers
- 6.6. References
- PART 3: Architecture Examples and Tools for MPSoC
- 7 SESAM: A Comprehensive Framework for Cyber-Physical System Prototyping
- 7.1. Introduction
- 7.2. An overview of the SESAM platform
- 7.2.1. Multi-abstraction system prototyping
- 7.2.2. Assessing extra-functional system properties
- 7.3. VPSim: fast and easy virtual prototyping
- 7.3.1. Writing peripherals in Python
- 7.3.2. The ModelProvider interface
- 7.3.3. QEMU support
- 7.3.4. Online simulation monitoring
- 7.3.5. Acceleration methods
- 7.4. Hybrid prototyping
- 7.4.1. Co-simulation mode
- 7.4.2. Co-emulation mode
- 7.4.3. Runtime performance analysis and debugging features
- 7.5. FMI for co-simulation
- 7.5.1. Functional mock-up interface
- 7.5.2. VPSim integration in FMI co-simulation
- 7.6. Conclusion
- 7.7. References
- 8 StaccatoLab: A Programming and Execution Model for Large-scale Dataflow Computing
- 8.1. Introduction
- 8.2. Static dataflow
- 8.2.1. Synchronous dataflow
- 8.2.2. Cyclo-static dataflow
- 8.2.3. Dataflow graph transformations
- 8.3. Dynamic dataflow
- 8.3.1. Data-dependent dataflow
- 8.3.2. Non-determinate dataflow
- 8.4. Dataflow execution models
- 8.4.1. A brief review of dataflow theory
- 8.4.2. The StaccatoLab execution model
- 8.5. StaccatoLab
- 8.5.1. Dataflow graph description and analysis
- 8.5.2. Verilog synthesis
- 8.6. Large-scale dataflow computing?
- 8.6.1. What kind of applications?
- 8.6.2. Why effective?
- 8.6.3. Why efficient?
- 8.7. Acknowledgments
- 8.8. References
- 9 Smart Cameras and MPSoCs
- 9.1. Introduction
- 9.2. Early VLSI video processors
- 9.3. Video signal processors
- 9.4. Accelerators
- 9.5. From VSP to MPSoC
- 9.6. Graphics processing units
- 9.7. Neural networks and tensor processing units
- 9.8. Conclusion
- 9.9. References
- 10. Software Compilation and Optimization Techniques for Heterogeneous Multi-core Platforms
- 10.1. Introduction
- 10.2. Dataflow modeling
- 10.2.1. General concepts
- 10.2.2. Process networks
- 10.2.3. C for process networks
- 10.3. Source-to-source-based compiler infrastructure
- 10.3.1. Design rationale
- 10.3.2. Implementation strategy
- 10.4. Software distribution
- 10.4.1. KPN analysis
- 10.4.2. Static KPN mapping
- 10.4.3. Hybrid KPN mapping
- 10.5. Results
- 10.5.1. Applications and experiences
- 10.5.2. Retargetability
- 10.6. Conclusion
- 10.7. References
- List of Authors
- Author Biographies
- Index
- EULA
1
From Challenges to Hardware Requirements for Wireless Communications Reaching 6G
Stefan A. DAMJANCEVIC1, Emil MATUS1, Dmitry UTYANSKY2, Pieter VAN DER WOLF3 and Gerhard P. FETTWEIS1, 4
1 Vodafone Chair Mobile, Communications Systems, TU Dresden, Germany
2 Synopsys, Saint Petersburg, Russia
3 Solutions Group, Synopsys, Inc., Eindhoven, The Netherlands
4 Barkhausen Institut, TU Dresden, Germany
Over the past few decades, we have seen rapid innovation in wireless communications. In particular, the IEEE 802.11 and 3GPP standardization organizations have driven data rates into the Gb/s range, enabling modern life, at home, at work and on the road. Societies of today have become dependent on this important infrastructure. The basis of this development is an infrastructure based on electronic circuits, which are driven, at heart, by very advanced multi-processor system-on-chip engines.
Firstly, we want to deliver a vision on what is to be expected from 6G, the next innovation wave of cellular technology. Cellular 1G was about delivering analogue voices, and digital 2G fixed it. The intention of 3G was to deliver data, but only 4G made it proficiently available for the service requirements. With 5G, we see the advent of the Tactile Internet, i.e. connecting remote controls not as point-to-point solutions but via a network. Will 6G be just a "fix" of issues left unsolved? We believe 6G will deliver truly more than this, and will also require many more sophisticated signal processing tasks.
Secondly, we want to analyze the computational tasks of 5G and beyond baseband processing, as well as their specification requirements. It becomes clear that the heterogeneity of computation cannot be mapped efficiently onto a homogeneous processor array. Instead, we need to find the right architecture for the right task. The reader is introduced to an extremely varied set of requirements as the services dramatically differ in terms of latency, data rate and reliability.
Thirdly, we want to give perspective and a sense of scale required from hardware for the previously determined corner workloads. We do this by implementing an example beyond 5G algorithm generalized frequency division multiplexing, with regard to those workloads, on a prototype software programmable single-instruction, multiple-data wide vector processing machine. Workloads alone are not sufficient to deduce adequate requirements for hardware (HW). To bridge the gap between workloads and HW requirements, we need to know how the 6G candidate waveform modulation translates workloads into HW requirements.
Conclusively, the performance-cost analysis shows a need for high flexibility. The low-end use case of the implemented algorithm easily fits within one 1 GHz 512 bit vector processor core requiring 1.01 - 5.39 MHz of the processor clock budget, therefore enabling seamless time multiplexing with other software (SW) kernels running on the core. The carrier aggregation (CA) high-end use case requires 921 - 5,505 MHz, which allows the prior clock-efficient version to fit on one 1 GHz 512 bit vector processor core. This sets the stage for the system designer to opt between a generalized vector processor or some more specialized HW accelerator engine, such as a dedicated (application-specific) HW accelerator or an application-specific instruction set processor (ASIP). Finally, the implemented algorithm running the multiple-input, multiple-output (MIMO) CA high-end use case would require a budget of 7.37 - 44.04 GHz, the theoretical equivalent of eight or forty-five 512 bit vector processor cores, making the high-end use case more suitable for execution on the dedicated HW accelerator or the ASIP, which were otherwise powered down. The use case corners demonstrate a high variability requirement from HW, which makes heterogeneous multi-processor system-on-chip (MPSoC) solutions ideal future-proof HW for beyond 5G. In this chapter, we present our key findings that connect the dots from vision to future HW in wireless communications.
1.1. Introduction
As we are writing this chapter in early 2020, it is obvious that there exists a gap between the conventional 5G vision (Fettweis 2012; NGMN Alliance 2015; Qualcomm 2016) and the deployed 5G. We do not have coordinated unmanned areal vehicles (UAV) groups humming over our cities like busy worker bees around hives (ARIB et al. 2016). We do not have critical vehicle to everything (V2X) communication with 1 ms end-to-end latency coordinated "emergency trajectory adjustment" (3GPP 2018d) keeping us safe, nor the smart infrastructure that would make traffic lights obsolete (Fettweis 2012). We do not have the cellular virtual reality (VR) and augmented reality (AR) (NGMN Alliance 2015) helping us to acquire and select important information about our environment when we explore new places. Let us investigate why is that so. How did we come into this situation, where are we now and what should we do to traverse this rift?
1G was a great step, which created the vision of ubiquitous voice telephony, but we needed 2G to deliver on the expectations created such as, for example, national and international roaming. The 3G standards were a great step towards ubiquitous cellular data, but we needed 4G to fix the problems. Now 5G should be an infliction point in bringing cellular data to new applications. However, do we need to use the 5G system to understand what is really needed, and have to wait for 6G to fix the issues? And are these fixes required to make the Tactile Internet a reality?
As we see 5G unfold, expectations on the economic and societal impact are very high. Many new opportunities for business will emerge with the new communications epoch. Besides Gb/s data rates, the Tactile Internet is the most highlighted promise of 5G, enabling remote control applications over cellular data. We will review opportunities and their technical requirements. This helps us to build an understanding, to detect missing pieces. It is of particular interest to see the broad set of chances in semiconductors unfolding before us, making the pathway to 6G maybe the next wild and open opportunity for entrepreneurship and change in company economics.
As of the first half of the 2010s, different sectors of the industry, research and, later, politicians, as well as regulatory bodies, overwhelmingly adopted and unanimously agreed that 5G was needed. The basic driver for creating the Tactile Internet vision for 5G was published in early 2014 (Fettweis 2014) and later acknowledged in (ARIB et al. 2016; 3GPP 2018d). The overall consensus on the need for 5G resulted in the typical standardization iterations of the 5G standard in 3GPP (2017, 2018c), landing firmly on the 5G stand-alone (3GPP 2019e, c, d). The main innovation, next to higher data rates, is the introduction of ultra-reliable low latency communications (URLLC) around the idea of the Tactile Internet, which again addresses a new domain not served by cellular data so far. As we slowly start understanding the true requirements and impact of URLLC, it turns out that 5G will not fully deliver a solution as required.
Given that 3GPP 5G NR specifications (3GPP 2019c, d) regarding handsets for frequency range 1 (FR1) (0.45 GHz - 6 GHz) and frequency range 2 (FR2) (24.25 GHz - 52.6 GHz) operating ranges exist, the MPSoCs, which can be scaled in data rate as well as latency, are still to be designed.
For the contemporary reader, this chapter offers an incremental contribution to the fulfillment of that vision, spanning the gap between 5G and 6G. For the future reader, this chapter offers a methodology of translating workloads via a specific algorithm to HW.
Section 1.2 shows the trends and analyzes the workloads defined by the standards. In addition, it gives lower and upper requirements to be considered when implementing a communications modem. In section 1.3, we give the reader a background on the 6G candidate waveform modulation generalised frequency division multiplexing (GFDM), develop a GFDM-associated dataflow processing graph and pseudo-code. Section 1.4 covers precision requirements, in which we explore required bit-lengths to represent data and satisfy 3GPP LTE/NR error requirements. Section 1.5 presents the implementation, GFDM vectorization variants, loop order variants and many properties that arise from loop and vectorization arrangements, such as the possibility of minimizing cycle counts for maximum throughput or minimizing the number of memory accesses for low-power operation.
1.2. Breadth of workloads
The first step towards estimating the HW requirements for a typical beyond 3GPP 5th Generation New Radio (5G) algorithm is sizing the span of workloads in terms of throughput and deadlines under which data processing has to finish. To study the matter, we go over the holistic vision and trends of what we expect in 6G, followed by an analysis of the key deployed 5G standard specifications. From the latter, we identify the far corners that stretch the workload requirement space, see how these corners fit into the vision and trends and provide numerical values for HW requirements of a future MPSoC. Finally, throughout the workload analysis, the emerging theme is the required high flexibility,...
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