Cardiac Patients Monitoring at a Distance

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Chapter 3.8 AT MEGA 8 MICROCONTROLLER:

The Atmel® AVR® ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. [.].
3.8.1 Pin Description:

VCC: Digital supply voltage. GND: Ground.
Port B (PB7.PB0)XTAL1/XTAL2/TOSC1/TOSC2: Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7.6 is used as TOSC2.1input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
Port C (PC5.PC0): Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pullup resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
PC6/RESET: If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is un programmed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running generate a Reset.
Port D (PD7.PD0): Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
RESET: Reset input. A low level on this pin for longer than the minimum pulse length will generate areset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
3.8.2 ATMEGA 8 Architecture:

The ATmega8 provides the following features: 8 Kbytes of In- System Programmable Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1 Kbyte of SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Two wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power downmode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base hile the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.
The ATmega8 is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program simulators, and evaluation kits. [.].
3.8.3 Memory Organization:

The ATmega8 provides the following features: 8 Kbytes of In- System Programmable Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1 Kbyte of SRAM.
3.8.4 Special Function Registers (SFR):

Special function registers are part of RAM memory. Their purpose is predefined by the manufacturer and cannot be changed therefore. Since their bits are physically connected to particular circuits within the microcontroller, such as A/D converter, serial communication module etc., any change of their state directly affects the operation of the microcontroller or some of the circuits.
3.8.5 Program Counter:

Program Counter is an engine running the program and points to the memory address containing the next instruction to execute. After each instruction execution, the value of the counter is incremented by 1. For this reason, the program executes only one instruction at a time just as it is written. However.the value of the program counter can be changed at any moment, which causes a "jump" to a new memory location.
3.8.6 Input/output ports (I/O Ports):

It has 23 Programmable I/O Lines, 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF and the Operating Voltages are 4.5V - 5.5V (ATmega8).
3.9 TARANG:

Tarang 2.4GHz Modules are suitable for adding wireless capability to any product with serial data interface. The modules require minimal power and provide reliable delivery of data between devices. The I/O interfaces provided with the Module help to directly fit into many industrial applications. The modules operate within the ISM 2.4 GHz frequency with 802.15.4 base band. [.].
A whip antenna is an antenna consisting of a single straight flexible wire or rod. The bottom end of the whip is connected to the radio receiver or transmitter. They are designed to be flexible so that they won't break off, and the name is derived from their whip-like motion when disturbed. Often whip antennas for portable radios are made of a series of interlocking telescoping metal tubes, so they can be retracted when not in use. Longer ones made for mounting on vehicles or structures are made of a flexible fiberglass rod surrounding a wire core, and can be up to 35 ft (10 m) long. Whips are the most common type of monopole antenna. These antennas are widely used for handheld radios such as cell phones, cordless phones, walkie-talkies,FM radios, boom boxes, Wifi enabled devices, and GPS receivers, and also attached to vehicles as the antennas for car radios and two way radios for police, fire and aircraft. Larger versions mounted on roofs or radio masts are used as base station antennas for police, fire, ambulance, taxi and other vehicle dispatchers.