System-on-Chip
Next generation electronics
1st Edition
Published on 1. November 2008
944 pages
978-1-84919-020-6 (ISBN)
Description
System-on-Chip (SoC) is believed to represent the next major market for microelectronics, and there is a considerable interest world-wide in developing effective methods and tools to support the SoC paradigm. The field of SoC is broad and expanding and at present the technical and technological literature about the overall state-of-the-art in SoC is dispersed across a wide spectrum of books, journals, and conference proceedings. This edited book is an attempt to provide a comprehensive and accessible source of state-of-the-art information on existing and emerging SoC key research areas. In particular, the book covers the general principles and ideas of designing, validating and testing complex embedded computing systems and their underlying tradeoffs. Twenty-five international research groups have contributed to the book. Each contribution has an up-to-date survey highlighting the key achievements and future trends. To facilitate the understanding of the various topics covered in the book, each chapter has some background covering the basic principles, and extensive list of references. To enhance the book readability, the chapters are grouped into eight parts, each part examining a particular theme of SoC, including system design, embedded software, power management, reconfigurable computing, network-on-chip, verification and test. The book will be of interest to graduate students, designers and managers working in Electronic and Computer engineering.
More details
Series
Language
English
Place of publication
Stevenage
United Kingdom
Target group
College/higher education
Professional and scholarly
ISBN-13
978-1-84919-020-6 (9781849190206)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
Book
01/2006
Institution of Engineering and Technology
€184.50
Shipment within 3-4 weeks
Person
Bashir M. Al-Hashimi is professor of Computer Engineering at the School of Electronics and Computer Science, University of Southampton, UK. Professor Al-Hashimi is Editor-in-Chief, IEE Proceedings: Computer and Digital Techniques. He is a Fellow of the IEE.
Content
Part 1: System-level design
Chapter 1: Multi-criteria decision making in embedded system design
Chapter 2: System-level performance analysis - the SymTA/S approach
Chapter 3: Analysis and optimisation of heterogeneous real-time embedded systems
Chapter 4: Hardware/software partitioning of operating systems: focus on deadlock avoidance
Chapter 5: Models of computation in the design process
Chapter 6: Architecture description languages for programmable embedded systems
Part 2: Embedded software
Chapter 7: Concurrent models of computation for embedded software
Chapter 8: Retargetable compilers and architecture exploration for embedded processors
Chapter 9: Software power optimisation
Part 3: Power reduction and management
Chapter 10: Power-efficient data management for dynamic applications
Chapter 11: Low power system scheduling, synthesis and displays
Chapter 12: Power minimisation techniques at the RT-level and below
Chapter 13: Leakage power analysis and reduction for nano-scale circuits
Part 4: Reconfigurable computing
Chapter 14: Reconfigurable computing: architectures and design methods
Part 5: Architectural synthesis
Chapter 15: CAD tools for embedded analogue circuits in mixed-signal integrated Systems-on-Chip
Chapter 16: Clock-less circuits and system synthesis
Part 6: Network-on-chip
Chapter 17: Network-on-chip architectures and design methods
Chapter 18: Asynchronous on-chip networks
Part 7: Simulation and verification
Chapter 19: Covalidation of complex hardware/software systems
Chapter 20: Hardware/software cosimulation from interface perspective
Chapter 21: System-level validation using formal techniques
Part 8: Manufacturing test
Chapter 22: Efficient modular testing and test resource partitioning for core-based SoCs
Chapter 23: On-chip test infrastructure design for optimal multi-site testing
Chapter 24: High-resolution flash time-to-digital conversion and calibration for system-on-chip testing
Chapter 25: Yield and reliability prediction for DSM circuits
Chapter 1: Multi-criteria decision making in embedded system design
Chapter 2: System-level performance analysis - the SymTA/S approach
Chapter 3: Analysis and optimisation of heterogeneous real-time embedded systems
Chapter 4: Hardware/software partitioning of operating systems: focus on deadlock avoidance
Chapter 5: Models of computation in the design process
Chapter 6: Architecture description languages for programmable embedded systems
Part 2: Embedded software
Chapter 7: Concurrent models of computation for embedded software
Chapter 8: Retargetable compilers and architecture exploration for embedded processors
Chapter 9: Software power optimisation
Part 3: Power reduction and management
Chapter 10: Power-efficient data management for dynamic applications
Chapter 11: Low power system scheduling, synthesis and displays
Chapter 12: Power minimisation techniques at the RT-level and below
Chapter 13: Leakage power analysis and reduction for nano-scale circuits
Part 4: Reconfigurable computing
Chapter 14: Reconfigurable computing: architectures and design methods
Part 5: Architectural synthesis
Chapter 15: CAD tools for embedded analogue circuits in mixed-signal integrated Systems-on-Chip
Chapter 16: Clock-less circuits and system synthesis
Part 6: Network-on-chip
Chapter 17: Network-on-chip architectures and design methods
Chapter 18: Asynchronous on-chip networks
Part 7: Simulation and verification
Chapter 19: Covalidation of complex hardware/software systems
Chapter 20: Hardware/software cosimulation from interface perspective
Chapter 21: System-level validation using formal techniques
Part 8: Manufacturing test
Chapter 22: Efficient modular testing and test resource partitioning for core-based SoCs
Chapter 23: On-chip test infrastructure design for optimal multi-site testing
Chapter 24: High-resolution flash time-to-digital conversion and calibration for system-on-chip testing
Chapter 25: Yield and reliability prediction for DSM circuits
