Integrated Circuit Manufacturability
The Art of Process and Design Integration
1st Edition
Published on 16. October 1998
Book
Hardback
336 pages
978-0-7803-3447-2 (ISBN)
Description
"INTEGRATED CIRCUIT MANUFACTURABILITY provides comprehensive coverage of the process and design variables that determine the ease and feasibility of fabrication (or manufacturability) of contemporary VLSI systems and circuits. This book progresses from semiconductor processing to electrical design to system architecture. The material provides a theoretical background as well as case studies, examining the entire design for the manufacturing path from circuit to silicon. Each chapter includes tutorial and practical applications coverage.
INTEGRATED CIRCUIT MANUFACTURABILITY illustrates the implications of manufacturability at every level of abstraction, including the effects of defects on the layout, their mapping to electrical faults, and the corresponding approaches to detect such faults. The reader will be introduced to key practical issues normally applied in industry and usually required by quality, product, and design engineering departments in today's design practices:
* Yield management strategies
* Effects of spot defects
* Inductive fault analysis and testing
* Fault-tolerant architectures and MCM testing strategies.
This book will serve design and product engineers both from academia and industry. It can also be used as a reference or textbook for introductory graduate-level courses on manufacturing."
INTEGRATED CIRCUIT MANUFACTURABILITY illustrates the implications of manufacturability at every level of abstraction, including the effects of defects on the layout, their mapping to electrical faults, and the corresponding approaches to detect such faults. The reader will be introduced to key practical issues normally applied in industry and usually required by quality, product, and design engineering departments in today's design practices:
* Yield management strategies
* Effects of spot defects
* Inductive fault analysis and testing
* Fault-tolerant architectures and MCM testing strategies.
This book will serve design and product engineers both from academia and industry. It can also be used as a reference or textbook for introductory graduate-level courses on manufacturing."
More details
Language
English
Place of publication
United States
Publishing group
John Wiley & Sons Inc
Target group
College/higher education
Professional and scholarly
Product notice
sewn/stitched
Cloth over boards
Dimensions
Height: 262 mm
Width: 185 mm
Thickness: 25 mm
Weight
807 gr
ISBN-13
978-0-7803-3447-2 (9780780334472)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Persons
About the Editors...
Jose Pineda de Gyvez is an associate professor in the Department of Electrical Engineering, holding a joint faculty appointment with the Department of Computer Science, at Texas A&M University. Dr. Pineda de Gyvez was associate editor of technology for IEEE Transactions on Semiconductor Manufacturing and associate editor for cellular neural networks for IEEE Transactions on Circuits and Systems: Part 1.
Dhiraj K. Pradhan is currently a visiting professor with the Department of Electrical Engineering at Stanford University (on leave from Texas A&M University.) Prior to joining Texas A&M, he served as professor and coordinator of computer engineering at the University of Massachusetts. Dr. Pradhan has contributed to VLSI CAD and test fault-tolerant computing, computer architecture, and parallel processing research with major publications in journals and conferences over the last 25 years.
Jose Pineda de Gyvez is an associate professor in the Department of Electrical Engineering, holding a joint faculty appointment with the Department of Computer Science, at Texas A&M University. Dr. Pineda de Gyvez was associate editor of technology for IEEE Transactions on Semiconductor Manufacturing and associate editor for cellular neural networks for IEEE Transactions on Circuits and Systems: Part 1.
Dhiraj K. Pradhan is currently a visiting professor with the Department of Electrical Engineering at Stanford University (on leave from Texas A&M University.) Prior to joining Texas A&M, he served as professor and coordinator of computer engineering at the University of Massachusetts. Dr. Pradhan has contributed to VLSI CAD and test fault-tolerant computing, computer architecture, and parallel processing research with major publications in journals and conferences over the last 25 years.
Content
Preface.
Introduction (Jose Pineda de Gyvez).
Defect Monitoring and Characterization (Eric Bruls).
Digital CMOS Fault Modeling and Inductive Fault Analysis (Manoj Sachdev).
Functional Yield Modeling (Gary C. Cheek and Geoff O'Donoghue).
Critical Area and Fault Probability Prediction (D.M.H. Walker).
Statistical Methods of Parametric Yield and Quality Enhancement (Maciej Styblinski).
Architectural Fault Tolerance (S.K. Tewksbury).
Design for Test and Manufacturability (Dhiraj Pradhan and Adit Singh).
Testing Solutions for MCM Manufacturing (Yervant Zorian).
Index.
About the Editors.
Introduction (Jose Pineda de Gyvez).
Defect Monitoring and Characterization (Eric Bruls).
Digital CMOS Fault Modeling and Inductive Fault Analysis (Manoj Sachdev).
Functional Yield Modeling (Gary C. Cheek and Geoff O'Donoghue).
Critical Area and Fault Probability Prediction (D.M.H. Walker).
Statistical Methods of Parametric Yield and Quality Enhancement (Maciej Styblinski).
Architectural Fault Tolerance (S.K. Tewksbury).
Design for Test and Manufacturability (Dhiraj Pradhan and Adit Singh).
Testing Solutions for MCM Manufacturing (Yervant Zorian).
Index.
About the Editors.