Verilog Designer's Library
Published on 22. July 1999
Book
Paperback/Softback
432 pages
978-0-13-081154-7 (ISBN)
Description
Ready-to-use building blocks for integrated circuit design.
Why start coding from scratch when you can work from this library of pre-tested routines, created by an HDL expert? There are plenty of introductory texts to describe the basics of Verilog, but Verilog Designer's Library is the only book that offers real, reusable routines that you can put to work right away.
Verilog Designer's Library organizes Verilog routines according to functionality, making it easy to locate the material you need. Each function is described by a behavioral model to use for simulation, followed by the RTL code you'll use to synthesize the gate-level implementation. Extensive test code is included for each function, to assist you with your own verification efforts.
Coverage includes:
Essential Verilog coding techniques
Basic building blocks of successful routines
State machines and memories
Practical debugging guidelines
Although Verilog Designer's Library assumes a basic familiarity with Verilog structure and syntax, it does not require a background in programming. Beginners can work through the book in sequence to develop their skills, while experienced Verilog users can go directly to the routines they need. Hardware designers, systems analysts, VARs, OEMs, software developers, and system integrators will find it an ideal sourcebook on all aspects of Verilog development.
Why start coding from scratch when you can work from this library of pre-tested routines, created by an HDL expert? There are plenty of introductory texts to describe the basics of Verilog, but Verilog Designer's Library is the only book that offers real, reusable routines that you can put to work right away.
Verilog Designer's Library organizes Verilog routines according to functionality, making it easy to locate the material you need. Each function is described by a behavioral model to use for simulation, followed by the RTL code you'll use to synthesize the gate-level implementation. Extensive test code is included for each function, to assist you with your own verification efforts.
Coverage includes:
Essential Verilog coding techniques
Basic building blocks of successful routines
State machines and memories
Practical debugging guidelines
Although Verilog Designer's Library assumes a basic familiarity with Verilog structure and syntax, it does not require a background in programming. Beginners can work through the book in sequence to develop their skills, while experienced Verilog users can go directly to the routines they need. Hardware designers, systems analysts, VARs, OEMs, software developers, and system integrators will find it an ideal sourcebook on all aspects of Verilog development.
More details
Language
English
Place of publication
Upper Saddle River
United States
Publishing group
Pearson Education (US)
Target group
College/higher education
Dimensions
Height: 180 mm
Width: 242 mm
Thickness: 30 mm
Weight
649 gr
ISBN-13
978-0-13-081154-7 (9780130811547)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Person
Bob Zeidman is the founder, president and CEO of The Chalkboard Network (www.chalknet.com), a company that provides training for high-tech professionals via the Internet. Previously, Bob was the president of Zeidman Consulting where he designed ASICs, FPGAs, and PC boards for various real-time systems. His clients included Apple Computer, Cisco Systems, Ricoh Systems, and Texas Instruments. He has written technical papers on hardware and software design methods, and has taught courses on Verilog, ASIC design, and FPGA design at conferences throughout the world. He holds a Master's degree from Stanford University and two Bachelor's degrees from Cornell University.
Content
I. CODING TECHNIQUES.
1. General Coding Techniques.
Code Structure. Comments. Do Not Use Disable Instructions.
2. Behavioral Coding Techniques.
Eliminate Periodic Instructions. Eliminate Event Order Dependencies.
3. RTL Coding Techniques.
Synchronous Design. Allowable Uses of Asynchronous Logic.
4. Synthesis Issues.
Correlated Unknown Signals. State Machines. Optimizing Out Terms. Always Blocks.
5. Simulation Issues.
Simulate The Corner Cases. Use Code Coverage Tools. Use The Triple Equals. Use The $display And $stop Statements.
II. BASIC BUILDING BLOCKS.
6. The J-K Flip Flop.
Behavioral Code. RTL Code. Simulation Code.
7. The Shift Register.
Behavioral Code. RTL Code. Simulation Code.
8. The Counter.
Behavioral Code. RTL Code. Simulation Code.
9. The Adder.
Behavioral Code. RTL Code. Simulation Code.
III. STATE MACHINES.
10. The Moore State Machine.
Behavioral Code. RTL Code. Simulation Code.
11. The Mealy State Machine.
Behavioral Code. RTL Code. Simulation Code.
12. The One-Hot State Machine for FPGAs.
RTL Code. Simulation Code.
IV. MISCELLANEOUS COMPLEX FUNCTIONS.
13. The Linear Feedback Shift Register (LFSR).
Behavioral Code. RTL Code. Simulation Code.
14. The Encrypter/Decrypter.
Behavioral Code. RTL Code. Simulation Code.
15. The Phase Locked Loop (PLL).
Behavioral Code. RTL Code. Simulation Code.
16. The Unsigned Integer Multiplier.
Behavioral Code. RTL Code. Simulation Code.
17. The Signed Integer Multiplier.
Behavioral Code. RTL Code. Simulation Code.
V. ERROR DETECTION AND CORRECTION.
18. The Parity Generator and Checker.
Implementation Code. Simulation Code.
19. Hamming Code Logic.
Implementation Code. Simulation Code.
20. The Checksum.
Implementation Code. Simulation Code.
21. The Cyclic Redundancy Check (CRC).
Behavioral Code. RTL Code. Simulation Code.
VI. MEMORIES.
22. The Random Access Memory (RAM).
Implementation Code. Simulation Code.
23. The Dual Port RAM.
Implementation Code. Simulation Code.
24. The Synchronous FIFO.
Behavioral Code. RTL Code. Simulation Code.
25. The Synchronizing FIFO.
Behavioral Code. RTL Code. Simulation Code.
VII. MEMORY CONTROLLERS.
26. The SRAM/ROM Controller.
Behavioral Code. RTL Code. Simulation Code.
27. The Synchronous SRAM Controller.
Behavioral Code. RTL Code. Simulation Code.
28. The DRAM Controller.
Behavioral Code. RTL Code. Simulation Code.
29. The Fast Page Mode DRAM Controller.
Behavioral Code. RTL Code. Simulation Code.
Appendix A: Resources.
Glossary.
Index.
1. General Coding Techniques.
Code Structure. Comments. Do Not Use Disable Instructions.
2. Behavioral Coding Techniques.
Eliminate Periodic Instructions. Eliminate Event Order Dependencies.
3. RTL Coding Techniques.
Synchronous Design. Allowable Uses of Asynchronous Logic.
4. Synthesis Issues.
Correlated Unknown Signals. State Machines. Optimizing Out Terms. Always Blocks.
5. Simulation Issues.
Simulate The Corner Cases. Use Code Coverage Tools. Use The Triple Equals. Use The $display And $stop Statements.
II. BASIC BUILDING BLOCKS.
6. The J-K Flip Flop.
Behavioral Code. RTL Code. Simulation Code.
7. The Shift Register.
Behavioral Code. RTL Code. Simulation Code.
8. The Counter.
Behavioral Code. RTL Code. Simulation Code.
9. The Adder.
Behavioral Code. RTL Code. Simulation Code.
III. STATE MACHINES.
10. The Moore State Machine.
Behavioral Code. RTL Code. Simulation Code.
11. The Mealy State Machine.
Behavioral Code. RTL Code. Simulation Code.
12. The One-Hot State Machine for FPGAs.
RTL Code. Simulation Code.
IV. MISCELLANEOUS COMPLEX FUNCTIONS.
13. The Linear Feedback Shift Register (LFSR).
Behavioral Code. RTL Code. Simulation Code.
14. The Encrypter/Decrypter.
Behavioral Code. RTL Code. Simulation Code.
15. The Phase Locked Loop (PLL).
Behavioral Code. RTL Code. Simulation Code.
16. The Unsigned Integer Multiplier.
Behavioral Code. RTL Code. Simulation Code.
17. The Signed Integer Multiplier.
Behavioral Code. RTL Code. Simulation Code.
V. ERROR DETECTION AND CORRECTION.
18. The Parity Generator and Checker.
Implementation Code. Simulation Code.
19. Hamming Code Logic.
Implementation Code. Simulation Code.
20. The Checksum.
Implementation Code. Simulation Code.
21. The Cyclic Redundancy Check (CRC).
Behavioral Code. RTL Code. Simulation Code.
VI. MEMORIES.
22. The Random Access Memory (RAM).
Implementation Code. Simulation Code.
23. The Dual Port RAM.
Implementation Code. Simulation Code.
24. The Synchronous FIFO.
Behavioral Code. RTL Code. Simulation Code.
25. The Synchronizing FIFO.
Behavioral Code. RTL Code. Simulation Code.
VII. MEMORY CONTROLLERS.
26. The SRAM/ROM Controller.
Behavioral Code. RTL Code. Simulation Code.
27. The Synchronous SRAM Controller.
Behavioral Code. RTL Code. Simulation Code.
28. The DRAM Controller.
Behavioral Code. RTL Code. Simulation Code.
29. The Fast Page Mode DRAM Controller.
Behavioral Code. RTL Code. Simulation Code.
Appendix A: Resources.
Glossary.
Index.