Cache Coherency Mechanisms in RISC-V Multicore Architectures
Cambridge Scholars Publishing
1st Edition
Published on 5. December 2025
Book
Paperback/Softback
155 pages
978-1-0364-6383-0 (ISBN)
Description
In the rapidly evolving world of multicore systems, ensuring cache coherency is crucial for maintaining data consistency and system performance. This book delves deep into the complexities of cache coherency in parallel computing environments, offering a comprehensive exploration of both snoop-based and directory-based protocols. Detailed insights are provided into various protocols, including MSI, MESI, MOSI, MOESI, and Write-Once, analysing their unique advantages and trade-offs. Leveraging the open-source RISC-V architecture, known for its scalability and modularity, the book presents the design and development of a scalable cache coherency fabric tailored for RISC-V multicore systems. Through detailed simulations using SystemVerilog and ModelSim, the book rigorously examines the fabric's ability to maintain memory consistency across multiple cores, providing valuable findings that contribute to the advancement of multicore processor design. Whether you are a researcher, engineer, or student, this book offers an essential guide to understanding and optimizing cache coherency in multicore systems.
More details
Language
English
ISBN-13
978-1-0364-6383-0 (9781036463830)
Schweitzer Classification
Other editions
Additional editions

Kim Ho Yeap | Wei Kun Tan
Cache Coherency Mechanisms in RISC-V Multicore Architectures
Book
03/2025
Cambridge Scholars Publishing
€100.46
Shipment within 15-20 days
Persons
Kim Ho Yeap, an associate professor at Universiti Tunku Abdul Rahman, Malaysia, and a senior member of IEEE, has published more than 180 peer-reviewed articles and 3 patents. Two of his published works impacted the design of the ALMA radio telescope's receiver optics. Yeap holds Chartered Engineer, Professional Engineer, and ASEAN Chartered Professional Engineer statuses, received teaching excellence and Intel Kudos awards, and secured close to 30 research grants.
Wei Kun Tan holds a bachelor's degree with Honours in Electronic and Communications Engineering and a master's in Engineering Electronic Systems from Universiti Tunku Abdul Rahman. Presently, he serves as a design verification engineer at Intel Altera.
Wei Kun Tan holds a bachelor's degree with Honours in Electronic and Communications Engineering and a master's in Engineering Electronic Systems from Universiti Tunku Abdul Rahman. Presently, he serves as a design verification engineer at Intel Altera.