Hardware and Software: Verification and Testing
10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014, Proceedings
Published on 6. November 2014
Book
Paperback/Softback
XVI, 302 pages
978-3-319-13337-9 (ISBN)
Description
This book constitutes the refereed proceedings of the 10th International Haifa Verification Conference, HVC 2014, held in Haifa, Israel, in November 2014.
The 17 revised full papers and 4 short papers presented were carefully reviewed and selected from 43 submissions. The papers cover a wide range of topics in the sub-fields of testing and verification applicable to software, hardware, and complex hybrid systems.
More details
Series
Edition
2014 ed.
Language
English
Place of publication
Cham
Switzerland
Publishing group
Springer International Publishing
Target group
Professional and scholarly
Research
Illustrations
78 s/w Abbildungen
XVI, 302 p. 78 illus.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 18 mm
Weight
487 gr
ISBN-13
978-3-319-13337-9 (9783319133379)
DOI
10.1007/978-3-319-13338-6
Schweitzer Classification
Other editions
Additional editions
Eran Yahav
Hardware and Software: Verification and Testing
10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014, Proceedings
E-Book
11/2014
Springer
€53.49
Available for download
Content
Using Coarse-Grained Abstractions to Verify Linearizability on TSO Architectures.- Enhancing Scenario Quality Using Quasi-Events.- Combined Bounded and Symbolic Model Checking for Incomplete Timed Systems.- DynaMate: Dynamically Inferring Loop Invariants for Automatic Full Functional Verification.- Generating Modulo-2 Linear Invariants for Hardware Model Checking.- Suraq - A Controller Synthesis Tool Using Uninterpreted Functions.- Synthesizing Finite-State Protocols from Scenarios and Requirements.- Automatic Error Localization for Software Using Deductive Verification.- Generating JML Specifications from Alloy Expressions.- Assume-Guarantee Abstraction Refinement Meets Hybrid Systems.- Handling TSO in Mechanized Linearizability Proofs.- Partial Quantifier Elimination.- Formal Verification of 800 Genetically Constructed Automata Programs: A Case Study.- A Framework to Synergize Partial Order Reduction with State Interpolation.- Reduction of Resolution Refutations and Interpolants via Subsumption.- Read, Write and Copy Dependencies for Symbolic Model Checking.- Efficient Combinatorial Test Generation Based on Multivalued Decision Diagrams.- Formal Verification of Secure User Mode Device Execution with DMA.- Supervisory Control of Discrete-Event Systems via IC3.- Partial-Order Reduction for Multi-core LTL Model Checking.- A Comparative Study of Incremental Constraint Solving Approaches in Symbolic Execution.