
Loop Tiling for Parallelism
Jingling Xue(Author)
Springer (Publisher)
Published on 12. October 2012
Book
Paperback/Softback
XIX, 256 pages
978-1-4613-6948-6 (ISBN)
Description
Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in
Loop Tiling for Parallelism
can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines.
Features and key topics:
Features and key topics:
- Detailed review of the mathematical foundations, including convex polyhedra and cones;
- Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability;
- Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation;
- A complete suite of techniques for generating SPMD code for a tiled loop nest;
- Up-to-date results on tile size and shape selection for reducing communication and improving parallelism;
- End-of-chapter references for further reading.
More details
Series
Edition
Softcover reprint of the original 1st ed. 2000
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Research
Illustrations
XIX, 256 p.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 16 mm
Weight
429 gr
ISBN-13
978-1-4613-6948-6 (9781461369486)
DOI
10.1007/978-1-4615-4337-4
Schweitzer Classification
Other editions
Additional editions


Jingling Xue
Loop Tiling for Parallelism
Book
08/2000
Kluwer Academic Publishers
€160.49
Shipment within 15-20 days
Content
I Mathematic Background and Loop Transformation.- 1. Mathematical Background.- 2. Nonsingular Transformations And Permutabidlity.- II Tiling as a Loop Transformation.- 3. Rectangular Tiling.- 4. Parallelepiped Tiling.- III Tiling for Distributed-Memory Machines.- 5. Spmd Code Generation.- 6. Communication-Minimal Tiling.- 7. Time-Minimal Tiling.