
Die-stacking Architecture
Morgan and Claypool Life Sciences (Publisher)
Published on 30. June 2015
Book
Paperback/Softback
127 pages
978-1-62705-765-3 (ISBN)
Description
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the ""memory wall"" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.
More details
Series
Language
English
Place of publication
San Rafael, CA
United States
Publishing group
Morgan & Claypool Publishers
Dimensions
Height: 235 mm
Width: 187 mm
Weight
333 gr
ISBN-13
978-1-62705-765-3 (9781627057653)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Content
- Preface
- Acknowledgments
- 3D Integration Technology
- Benefits of 3D Integration
- Fine-granularity 3D Processor Design
- Coarse-granularity 3D Processor Design
- 3D GPU Architecture
- 3D Network-on-Chip
- Thermal Analysis and Thermal-aware Design
- Cost Analysis for 3D ICs
- Conclusion
- Bibliography
- Acknowledgments
- 3D Integration Technology
- Benefits of 3D Integration
- Fine-granularity 3D Processor Design
- Coarse-granularity 3D Processor Design
- 3D GPU Architecture
- 3D Network-on-Chip
- Thermal Analysis and Thermal-aware Design
- Cost Analysis for 3D ICs
- Conclusion
- Bibliography