Modern VLSI Design
IP-Based Design
4th Edition
Published on 31. December 2008
Book
Hardback
656 pages
978-0-13-714500-3 (ISBN)
Description
The Number 1 VLSI Design Guide-Now Fully Updated for IP-Based Design and the Newest Technologies
Modern VLSI Design, Fourth Edition, offers authoritative, up-to-the-minute guidance for the entire VLSI design process-from architecture and logic design through layout and packaging. Wayne Wolf has systematically updated his award-winning book for today's newest technologies and highest-value design techniques. Wolf introduces powerful new IP-based design techniques at all three levels: gates, subsystems, and architecture. He presents deeper coverage of logic design fundamentals, clocking and timing, and much more. No other VLSI guide presents as much up-to-date information for maximizing performance, minimizing power utilization, and achieving rapid design turnarounds.
Coverage includes
All-new material on IP-based design
Extensive new coverage of networks-on-chips
New coverage of using FPGA fabrics to improve design flexibility
New material on image sensors, busses, Rent's Rule, pipelining, and more
Updated VLSI technology parameters reflecting the latest advances
Revised descriptions of HDLs and other VLSI design tools
Advanced techniques for overcoming bottlenecks and reducing crosstalk
Low-power design techniques for enhancing reliability and extending battery life
Testing solutions for every level of abstraction, from gates to architecture
Revamped end-of-chapter problems that fully reflect today's VLSI design challenges
Wolf introduces a top-down, systematic design methodology that begins with high-level models, extends from circuits to architecture, and facilitates effective testing. Along the way, he brings together all the skills VLSI design professionals will need to create tomorrow's state-of-the-art devices.
Modern VLSI Design, Fourth Edition, offers authoritative, up-to-the-minute guidance for the entire VLSI design process-from architecture and logic design through layout and packaging. Wayne Wolf has systematically updated his award-winning book for today's newest technologies and highest-value design techniques. Wolf introduces powerful new IP-based design techniques at all three levels: gates, subsystems, and architecture. He presents deeper coverage of logic design fundamentals, clocking and timing, and much more. No other VLSI guide presents as much up-to-date information for maximizing performance, minimizing power utilization, and achieving rapid design turnarounds.
Coverage includes
All-new material on IP-based design
Extensive new coverage of networks-on-chips
New coverage of using FPGA fabrics to improve design flexibility
New material on image sensors, busses, Rent's Rule, pipelining, and more
Updated VLSI technology parameters reflecting the latest advances
Revised descriptions of HDLs and other VLSI design tools
Advanced techniques for overcoming bottlenecks and reducing crosstalk
Low-power design techniques for enhancing reliability and extending battery life
Testing solutions for every level of abstraction, from gates to architecture
Revamped end-of-chapter problems that fully reflect today's VLSI design challenges
Wolf introduces a top-down, systematic design methodology that begins with high-level models, extends from circuits to architecture, and facilitates effective testing. Along the way, he brings together all the skills VLSI design professionals will need to create tomorrow's state-of-the-art devices.
More details
Edition
4th edition
Language
English
Place of publication
Upper Saddle River
United States
Publishing group
Pearson Education (US)
Target group
Professional and scholarly
Dimensions
Height: 239 mm
Width: 184 mm
Thickness: 37 mm
Weight
1110 gr
ISBN-13
978-0-13-714500-3 (9780137145003)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Previous edition
Book
01/2002
3rd Edition
Addison Wesley
€73.64
Article exhausted; check for reprint
Person
Wayne Wolf is Rhesa "Ray" S. Farmer Jr. Distinguished Chair in Embedded Computing Systems and Georgia Research Alliance Eminent Scholar at the Georgia Institute of Technology. Before joining Georgia Tech, he was with Princeton University from 1989 to 2007 and AT&T Bell Laboratories from 1984 to 1989. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University in 1980, 1981, and 1984, respectively. His research interests include VLSI systems, embedded computing, cyber-physical systems, and embedded computer vision. He has chaired several conferences, including CODES, EMSOFT, CASES, and ICCD. He was founding editor-in-chief ofACM Transactions on Embedded Computing Systems and founding co-editor-in-chief of Design Automation for Embedded Systems. He is a Fellow of the ACM and IEEE. He received the ASEE/CSE and HP Frederick E. Terman Award in 2003 and the IEEE Circuits and Systems Education Award in 2006.
Content
Preface to the Fourth Edition xv
Preface to the Third Edition xvii
Preface to the Second Edition xviii
Preface xix
About the Author xxii
Chapter 1: Digital Systems and VLSI 1
1.1 Why Design Integrated Circuits? 3
1.2 Integrated Circuit Manufacturing 5
1.3 CMOS Technology 18
1.4 Integrated Circuit Design Techniques 21
1.5 IP-Based Design 33
1.6 A Look into the Future 40
1.7 Summary 41
1.8 References 42
1.9 Problems 42
Chapter 2: Fabrication and Devices 43
2.1 Introduction 45
2.2 Fabrication Processes 45
2.3 Transistors 52
2.4 Wires and Vias 73
2.5 Fabrication Theory and Practice 84
2.6 Reliability 98
2.7 Layout Design and Tools 103
2.8 References 119
2.9 Problems 120
Chapter 3: Logic Gates 123
3.1 Introduction 125
3.2 Combinational Logic Functions 125
3.3 Static Complementary Gates 128
3.4 Switch Logic 157
3.5 Alternative Gate Circuits 159
3.6 Low-Power Gates 169
3.7 Delay through Resistive Interconnect 175
3.8 Delay through Inductive Interconnect 187
3.9 Design-for-Yield 193
3.10 Gates as IP 195
3.11 References 198
3.12 Problems 199
Chapter 4: Combinational Logic Networks 205
4.1 Introduction 207
4.2 Standard Cell-Based Layout 207
4.3 Combinational Network Delay 219
4.4 Logic and Interconnect Design 235
4.5 Power Optimization 246
4.6 Switch Logic Networks 251
4.7 Combinational Logic Testing 255
4.8 References 262
4.9 Problems 262
Chapter 5: Sequential Machines 267
5.1 Introduction 269
5.2 Latches and Flip-Flops 269
5.3 Sequential Systems and Clocking Disciplines 281
5.4 Performance Analysis 292
5.5 Clock Generation 310
5.6 Sequential System Design 312
5.7 Power Optimization 329
5.8 Design Validation 330
5.9 Sequential Testing 332
5.10 References 340
5.11 Problems 340
Chapter 6: Subsystem Design 345
6.1 Introduction 347
6.2 Combinational Shifters 349
6.3 Adders 352
6.4 ALUs 360
6.5 Multipliers 360
6.6 High-Density Memory 369
6.7 Image Sensors 382
6.8 Field-Programmable Gate Arrays 385
6.9 Programmable Logic Arrays 387
6.10 Buses and Networks-on-Chips 391
6.11 Data Paths 415
6.12 Subsystems as IP 417
6.13 References 422
6.14 Problems 422
Chapter 7: Floorplanning 425
7.1 Introduction 427
7.2 Floorplanning Methods 427
7.3 Global Interconnect 439
7.4 Floorplan Design 450
7.5 Off-Chip Connections 452
7.6 References 461
7.7 Problems 462
Chapter 8: Architecture Design 471
8.1 Introduction 473
8.2 Hardware Description Languages 473
8.3 Register-Transfer Design 495
8.4 Pipelining 509
8.5 High-Level Synthesis 518
8.6 Architectures for Low Power 539
8.7 GALS Systems 544
8.8 Architecture Testing 545
8.9 IP Components 550
8.10 Design Methodologies 551
8.11 Multiprocessor System-on-Chip Design 559
8.12 References 565
8.13 Problems 565
Appendix A: A Chip Designer's Lexicon 571
Appendix B: Hardware Description Languages 589
B.1 Introduction 589
B.2 Verilog 589
B.3 VHDL 594
References 599
Index 613
Preface to the Third Edition xvii
Preface to the Second Edition xviii
Preface xix
About the Author xxii
Chapter 1: Digital Systems and VLSI 1
1.1 Why Design Integrated Circuits? 3
1.2 Integrated Circuit Manufacturing 5
1.3 CMOS Technology 18
1.4 Integrated Circuit Design Techniques 21
1.5 IP-Based Design 33
1.6 A Look into the Future 40
1.7 Summary 41
1.8 References 42
1.9 Problems 42
Chapter 2: Fabrication and Devices 43
2.1 Introduction 45
2.2 Fabrication Processes 45
2.3 Transistors 52
2.4 Wires and Vias 73
2.5 Fabrication Theory and Practice 84
2.6 Reliability 98
2.7 Layout Design and Tools 103
2.8 References 119
2.9 Problems 120
Chapter 3: Logic Gates 123
3.1 Introduction 125
3.2 Combinational Logic Functions 125
3.3 Static Complementary Gates 128
3.4 Switch Logic 157
3.5 Alternative Gate Circuits 159
3.6 Low-Power Gates 169
3.7 Delay through Resistive Interconnect 175
3.8 Delay through Inductive Interconnect 187
3.9 Design-for-Yield 193
3.10 Gates as IP 195
3.11 References 198
3.12 Problems 199
Chapter 4: Combinational Logic Networks 205
4.1 Introduction 207
4.2 Standard Cell-Based Layout 207
4.3 Combinational Network Delay 219
4.4 Logic and Interconnect Design 235
4.5 Power Optimization 246
4.6 Switch Logic Networks 251
4.7 Combinational Logic Testing 255
4.8 References 262
4.9 Problems 262
Chapter 5: Sequential Machines 267
5.1 Introduction 269
5.2 Latches and Flip-Flops 269
5.3 Sequential Systems and Clocking Disciplines 281
5.4 Performance Analysis 292
5.5 Clock Generation 310
5.6 Sequential System Design 312
5.7 Power Optimization 329
5.8 Design Validation 330
5.9 Sequential Testing 332
5.10 References 340
5.11 Problems 340
Chapter 6: Subsystem Design 345
6.1 Introduction 347
6.2 Combinational Shifters 349
6.3 Adders 352
6.4 ALUs 360
6.5 Multipliers 360
6.6 High-Density Memory 369
6.7 Image Sensors 382
6.8 Field-Programmable Gate Arrays 385
6.9 Programmable Logic Arrays 387
6.10 Buses and Networks-on-Chips 391
6.11 Data Paths 415
6.12 Subsystems as IP 417
6.13 References 422
6.14 Problems 422
Chapter 7: Floorplanning 425
7.1 Introduction 427
7.2 Floorplanning Methods 427
7.3 Global Interconnect 439
7.4 Floorplan Design 450
7.5 Off-Chip Connections 452
7.6 References 461
7.7 Problems 462
Chapter 8: Architecture Design 471
8.1 Introduction 473
8.2 Hardware Description Languages 473
8.3 Register-Transfer Design 495
8.4 Pipelining 509
8.5 High-Level Synthesis 518
8.6 Architectures for Low Power 539
8.7 GALS Systems 544
8.8 Architecture Testing 545
8.9 IP Components 550
8.10 Design Methodologies 551
8.11 Multiprocessor System-on-Chip Design 559
8.12 References 565
8.13 Problems 565
Appendix A: A Chip Designer's Lexicon 571
Appendix B: Hardware Description Languages 589
B.1 Introduction 589
B.2 Verilog 589
B.3 VHDL 594
References 599
Index 613