Digital VLSI Design with Verilog
A Textbook from Silicon Valley Technical Institute
Published on 1. August 2008
Book
Hardback
XXIV, 436 pages
978-1-4020-8445-4 (ISBN)
Description
Verilog and its usage has come a long way since its original invention in the mid-80s by Phil Moorby. At the time the average design size was around ten thousand gates, and simulation to validate the design was its primary usage. But between then and now designs have increased dramatically in size, and automatic logic synthesis from RTL has become the standard design ?ow for most design. Indeed, the language has evolved and been re-standardized too. Overtheyears,manybookshavebeenwrittenaboutVerilog.Myown,coauthored with Phil Moorby, had the goal of de?ning the language and its usage, providing - amples along the way. It has been updated with ?ve new editions as the language and its usage evolved. However this new book takes a very different and unique view; that of the designer. John Michael Williams has a long history of working and teaching in the ?eld of IC and ASIC design. He brings an indepth presentation of Verilog and how to use it with logic synthesis tools; no other Verilog book has dealt with this topic as deeply as he has. If you need to learn Verilog and get up to speed quickly to use it for synthesis, this book is for you. It is sectioned around a set of lessons including presentation and explanation of new concepts and approaches to design, along with lab sessions.
More details
Edition
2008
Language
English
Place of publication
Dordrecht
Netherlands
Target group
College/higher education
Professional and scholarly
Research
Product notice
Laminated cover
Illustrations
biography
Dimensions
Height: 23.5 cm
Width: 15.5 cm
Thickness: 25 mm
Weight
847 gr
ISBN-13
978-1-4020-8445-4 (9781402084454)
DOI
10.1007/978-1-4020-8446-1
Schweitzer Classification
Other editions
New editions
John Michael Williams
Digital VLSI Design with Verilog
A Textbook from Silicon Valley Polytechnic Institute
Book
07/2014
2nd Edition
Springer
€181.89
Shipment within 10-15 days
Additional editions
E-Book
06/2008
1st Edition
Springer
€117.69
Available for download
Persons
Content
FOREWORD. PREFACE.
INTRODUCTION. 1. Course Description. 2. Using this book. References.
1. WEEK 1 CLASS 1. 1.1. Introductory Lab 1. 1.2. Verilog vectors. 1.3. Operator Lab 2. 1.4. First-Day Wrapup.
2. WEEK 1 CLASS 2. 2.1. More Language Constructs. 2.2. Parameter and Conversion Lab 3. 2.3. Procedural control. 2.4. Nonblocking Control Lab 4.
3. WEEK 2 CLASS 1. 3.1. Net Types, Simulation, and Scan. 3.2. Simple Scan Lab 5.
4. WEEK 2 CLASS 2. 4.1. PLLs and the SerDes Project. 4.2. PLL Clock Lab 6.
5. WEEK 3 CLASS 1. 5.1. Data Storage and Verilog Arrays. 5.2. Memory Lab 7.
6. WEEK 3 CLASS 2. 6.1. Counter Types and Structures. 6.2. Counter Lab 8.
7. WEEK 4 CLASS 1. 7.1. Contention and Operator Precedence. 7.2. Digital Basics: Three-State Buffer and Decoder. 7.3. Strength and Contention Lab 9. 7.4. Back to the PLL and the SerDes. 7.5. PLL Behavioral Lock-In Lab 10.
8. WEEK 4 CLASS 2. 8.1. State Machine and FIFO design. 8.2. FIFO Lab 11.
9. WEEK 5 CLASS 1. 9.1. Rise-Fall Delays and Event Scheduling. 9.2. Scheduling Lab 12.
10. WEEK 5 CLASS 2. 10.1. Built-in Gates and Net Types. 10.2. Netlist Lab 13.
11. WEEK 6 CLASS 1. 11.1. Procedural Control and Concurrency. 11.2. Concurrency Lab 14.
12. WEEK 6 CLASS 2. 12.1. Hierarchical Names and generate Blocks. 12.2. Generate Lab 15.
13. WEEK 7 CLASS 1. 13.1. Serial-Parallel Conversion. 13.2. Lab Preface: The Deserialization Decoder. 13.3. Serial-Parallel Lab 16.
14. WEEK 7 CLASS 2. 14.1. UDPs, Timing Triplets, and Switch-level Models. 14.2. Component Lab 17.
15. WEEK 8 CLASS 1. 15.1. Parameter Types and Module Connection. 15.2. Connection Lab 18. 15.3. Hierarchical Names and Design Partitions. 15.4. Hierarchy Lab 19.
16. WEEK 8 CLASS 2. 16.1. Verilog configurations. 16.2. Timing Arcs and specify Delays. 16.3. Timing Lab 20.
17. WEEK 9 CLASS 1. 17.1. Timing Checks and Pulse Controls. 17.2. Timing Check Lab 21.
18. WEEK 9 CLASS 2. 18.1. The Sequential Deserializer. 18.2. PLL Redesign. 18.3. Sequential Deserializer I Lab 22.
19. WEEK 10 CLASS 1. 19.1. The Concurrent Deserializer. 19.2. Concurrent Deserializer II Lab 23.
20. WEEK 10 CLASS 2. 20.1. The Serializer and The SerDes. 20.2. SerDes Lab 24.
21. WEEK 11 CLASS 1. 21.1. Design for Test (DFT). 21.2. Scan and BIST Lab 25. 21.3. DFT for a Full-Duplex SerDes. 21.4. Tested SerDes Lab 26.
22. WEEK 11 CLASS 2. 22.1. SDF Back-Annotation. 22.2. SDF Lab 27.
23. WEEK 12 CLASS 1. 23.1. Wrap-up: The Verilog Language. 23.2. Continued Lab Work (Lab 23 or later).
24. WEEK 12 CLASS 2. 24.1. Deep-Submicron Problems and Verification. 24.2. Continued Lab Work (Lab 23 or later).
INDEX.
INTRODUCTION. 1. Course Description. 2. Using this book. References.
1. WEEK 1 CLASS 1. 1.1. Introductory Lab 1. 1.2. Verilog vectors. 1.3. Operator Lab 2. 1.4. First-Day Wrapup.
2. WEEK 1 CLASS 2. 2.1. More Language Constructs. 2.2. Parameter and Conversion Lab 3. 2.3. Procedural control. 2.4. Nonblocking Control Lab 4.
3. WEEK 2 CLASS 1. 3.1. Net Types, Simulation, and Scan. 3.2. Simple Scan Lab 5.
4. WEEK 2 CLASS 2. 4.1. PLLs and the SerDes Project. 4.2. PLL Clock Lab 6.
5. WEEK 3 CLASS 1. 5.1. Data Storage and Verilog Arrays. 5.2. Memory Lab 7.
6. WEEK 3 CLASS 2. 6.1. Counter Types and Structures. 6.2. Counter Lab 8.
7. WEEK 4 CLASS 1. 7.1. Contention and Operator Precedence. 7.2. Digital Basics: Three-State Buffer and Decoder. 7.3. Strength and Contention Lab 9. 7.4. Back to the PLL and the SerDes. 7.5. PLL Behavioral Lock-In Lab 10.
8. WEEK 4 CLASS 2. 8.1. State Machine and FIFO design. 8.2. FIFO Lab 11.
9. WEEK 5 CLASS 1. 9.1. Rise-Fall Delays and Event Scheduling. 9.2. Scheduling Lab 12.
10. WEEK 5 CLASS 2. 10.1. Built-in Gates and Net Types. 10.2. Netlist Lab 13.
11. WEEK 6 CLASS 1. 11.1. Procedural Control and Concurrency. 11.2. Concurrency Lab 14.
12. WEEK 6 CLASS 2. 12.1. Hierarchical Names and generate Blocks. 12.2. Generate Lab 15.
13. WEEK 7 CLASS 1. 13.1. Serial-Parallel Conversion. 13.2. Lab Preface: The Deserialization Decoder. 13.3. Serial-Parallel Lab 16.
14. WEEK 7 CLASS 2. 14.1. UDPs, Timing Triplets, and Switch-level Models. 14.2. Component Lab 17.
15. WEEK 8 CLASS 1. 15.1. Parameter Types and Module Connection. 15.2. Connection Lab 18. 15.3. Hierarchical Names and Design Partitions. 15.4. Hierarchy Lab 19.
16. WEEK 8 CLASS 2. 16.1. Verilog configurations. 16.2. Timing Arcs and specify Delays. 16.3. Timing Lab 20.
17. WEEK 9 CLASS 1. 17.1. Timing Checks and Pulse Controls. 17.2. Timing Check Lab 21.
18. WEEK 9 CLASS 2. 18.1. The Sequential Deserializer. 18.2. PLL Redesign. 18.3. Sequential Deserializer I Lab 22.
19. WEEK 10 CLASS 1. 19.1. The Concurrent Deserializer. 19.2. Concurrent Deserializer II Lab 23.
20. WEEK 10 CLASS 2. 20.1. The Serializer and The SerDes. 20.2. SerDes Lab 24.
21. WEEK 11 CLASS 1. 21.1. Design for Test (DFT). 21.2. Scan and BIST Lab 25. 21.3. DFT for a Full-Duplex SerDes. 21.4. Tested SerDes Lab 26.
22. WEEK 11 CLASS 2. 22.1. SDF Back-Annotation. 22.2. SDF Lab 27.
23. WEEK 12 CLASS 1. 23.1. Wrap-up: The Verilog Language. 23.2. Continued Lab Work (Lab 23 or later).
24. WEEK 12 CLASS 2. 24.1. Deep-Submicron Problems and Verification. 24.2. Continued Lab Work (Lab 23 or later).
INDEX.