
Advanced AES Core
Emulation of verilog HDL into FPGA core
LAP Lambert Academic Publishing
Published on 14. March 2014
Book
Paperback/Softback
116 pages
978-3-659-16180-3 (ISBN)
Description
This book emphasized on FPGA design to develop AES CORE using verilog HDL. Mainly the work focus on 5 modules like, key generation, shift rows, mix columns, xoring module and top module- integration. All these modules are authorized in verilog HDL language. The key generation module generates required keys from the given key. The left circular shift operation is performed by shift rows. The mix columns perform the matrix multiplication with constant matrix. Xoring module specifies the xoring the text data with the key. The top module indicates the integration of all modules and it is treated as the AES Core. Prior to AES, Data Encryption Standard (DES) is a widely used method of data encryption using a private (secret) key that was so difficult to break. With the Triple DES implementation of DES, there are 5.1 * 10^33 or more possible encryption keys that can be used.
More details
Language
English
Product notice
Paperback (trade)
Unsewn / adhesive bound
Dimensions
Height: 220 mm
Width: 150 mm
Thickness: 8 mm
Weight
191 gr
ISBN-13
978-3-659-16180-3 (9783659161803)
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Schweitzer Classification
Persons
M.Tech Electronics Communication EngineeringLecturer, Shree Vithal Education And Research Institute COEP,Pandharpur