Architecture Exploration of FPGA Based Accelerators for BioInformatics Applications
Published on 14. March 2016
Book
Hardback
XV, 122 pages
978-981-10-0589-3 (ISBN)
Description
This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.
More details
Series
Edition
1st ed. 2016
Language
English
Place of publication
Singapore
Singapore
Target group
Professional and scholarly
Illustrations
14 s/w Abbildungen, 40 farbige Abbildungen
XV, 122 p. 54 illus., 40 illus. in color.
Dimensions
Height: 241 mm
Width: 160 mm
Thickness: 13 mm
Weight
409 gr
ISBN-13
978-981-10-0589-3 (9789811005893)
DOI
10.1007/978-981-10-0591-6
Schweitzer Classification
Other editions
Additional editions
B. Sharat Chandra Varma | Kolin Paul | M. Balakrishnan
Architecture Exploration of FPGA Based Accelerators for BioInformatics Applications
Book
04/2018
Springer
€106.99
Shipment within 15-20 days
B. Sharat Chandra Varma | Kolin Paul | M. Balakrishnan
Architecture Exploration of FPGA Based Accelerators for BioInformatics Applications
E-Book
03/2016
Springer
€96.29
Available for download
Persons
B. Sharat Chandra Varma is Research Associate in the Department of Electrical & Electronic Engineering at The University of Hong Kong, Hong Kong. He obtained his PhD from IIT Delhi, New Delhi. He completed his B.E. (2003) from Visvesvaraya Technological University Karnataka and MSc. (2007) from Manipal University, Karnataka. His research interest areas are re-configurable computing, FPGA, hardware-software co-design, hardware accelerators, and computer architecture. Dr. Varma has over 10 years of research and industrial experience and has several journal publications to his credit.
Kolin Paul is presently Associate Professor with the department of Computer Science and Engineering at Indian Institute of Technology Delhi, New Delhi. His academic degrees include M.Sc. (1995) from Jadavpur University and Ph.D. (2002) from Bengal Engineering College, Calcutta, India. Dr. Paul has several papers published in refereed journal and conference proceedings.
M. Balakrishnan isa Professor in the CSE Department at IIT Delhi, New Delhi, India. He completed his PhD in 1984 from IIT Delhi. He has 16 journal articles, 63 refereed conference publications, one book chapter and two patents to his credit. Dr. Balakrishnan has been a part of many research projects and consultancies from leading EDA/VLSI companies. He is a reviewer for major international journals, a member of key academic bodies. He has supervised 8 PhDs, 3 MS(R) and 78 M.Tech students. His areas of specialization are behavioral and system level synthesis, system level design and modeling, computer architecture, hardware-software co-design, embedded system design, and assistive devices for the visually impaired.
Kolin Paul is presently Associate Professor with the department of Computer Science and Engineering at Indian Institute of Technology Delhi, New Delhi. His academic degrees include M.Sc. (1995) from Jadavpur University and Ph.D. (2002) from Bengal Engineering College, Calcutta, India. Dr. Paul has several papers published in refereed journal and conference proceedings.
M. Balakrishnan isa Professor in the CSE Department at IIT Delhi, New Delhi, India. He completed his PhD in 1984 from IIT Delhi. He has 16 journal articles, 63 refereed conference publications, one book chapter and two patents to his credit. Dr. Balakrishnan has been a part of many research projects and consultancies from leading EDA/VLSI companies. He is a reviewer for major international journals, a member of key academic bodies. He has supervised 8 PhDs, 3 MS(R) and 78 M.Tech students. His areas of specialization are behavioral and system level synthesis, system level design and modeling, computer architecture, hardware-software co-design, embedded system design, and assistive devices for the visually impaired.
Content
Introduction.- Related Work.- Methodology for Implementing Accelerators.- FPGA based Acceleration of Protein Docking.- FPGA based Acceleration of De Novo Genome Assembly.- Design of Accelerators with HEBs.- System Level Design Space Exploration.- Future Directions.