Designing 2D and 3D Network-on-Chip Architectures
Published on 23. August 2016
Book
Paperback/Softback
XIII, 265 pages
978-1-4939-4550-4 (ISBN)
Description
This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.
More details
Edition
Softcover reprint of the original 1st ed. 2014
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Illustrations
79 farbige Abbildungen, 65 s/w Abbildungen
XIII, 265 p. 144 illus., 79 illus. in color.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 16 mm
Weight
429 gr
ISBN-13
978-1-4939-4550-4 (9781493945504)
DOI
10.1007/978-1-4614-4274-5
Schweitzer Classification
Other editions
Additional editions
Konstantinos Tatas | Kostas Siozios | Dimitrios Soudris
Designing 2D and 3D Network-on-Chip Architectures
Book
10/2013
1st Edition
Springer
€106.99
Shipment within 15-20 days
Content
Part I: Network-on-Chip Design Methodology.- Network-on-Chip Technology: A Paradigm Shift.- NoC Modeling and Topology Exploration.- Communication Architecture.- Power and Thermal Effects and Management.- NoC-based System Integration.- NoC Verification and Testing.- The Spidergon STNoC.- Middleware Memory Management in NoC.- On Designing 3-D Platforms.- The SYSMANTIC NoC Design and Prototyping Framework.- Part II: Suggested Projects.- Projects on Network-on Chip.