Embedded Computer Systems: Architectures, Modeling, and Simulation

.- Simulation, Emulation, and Design Space Exploration .

.- Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms.

.- Optimizing Binary and Ternary Neural Network Inference on RRAM Cross bars using CIM-Explorer.

.- qGAMMA: A Framework for Optimal DNN Mapping on Multi-Precision Accelerators.

.- Leveraging SystemC-TLM-based Virtual Prototypes for Embedded Soft ware Fuzzing.

.- HMOD: A CPU Simulator Based on an Agile Simulation Methodology.

.- Generation of a QEMU Based Instruction Set Simulator from a Processor Description in OpenVADL.

.- Security .

.- Prototyping Custom Hardware Performance Counters in gem5 Simulator: A Framework for RISC-V Side-Channel Attack Assessment.

.- Quantifying Overheads for Secure Remote Configuration of eFPGA-augmented SoCs.

.- RISC-V based Vectorization of Classic McEliece Key Generation.

.- Tools and Frameworks .

.- LearnCNM2Predict: Transfer Learning-based Performance Model for CNM Systems.

.- Beyond the Shadows: A Deep Dive into Profiling Modern Mixed-Modal and Multi-Modal Transformer Models.

.- Modular and Composable Framework for Multipurpose Monitoring in Heterogeneous FPGA-Based Systems.

.- A High-Level Compiler Integration Approach for Deep Learning Accelerators Supporting Abstraction and Optimization.

.- SW Generation for Embedded Systems with Low-Cost LLMs: A Multi Agent Approach.

.- ARISE: Automating RISC-V Instruction Set Extension.

.- Reliable and Real-Time Systems .

.- The HOT-RISC-V: A High-Operating-Temperature RISC-V Architecture for Extreme Conditions.

.- Evaluating Microarchitectural Hardware Fault Detection for Application Specific Requirements.

.- AnTi-MiCS: Analytical Framework for Bounding Time in Embedded Mixed Criticality Systems .

.- High Performance and Time Predictable Architectures .

.- GEYSER: A Design Generation Framework for Automated Large-Scale Accelerator Integration.

.- Shavette: Safe Undervolting of Neural Network Accelerators via Algorithm level Error Detection.

.- A Time-Predictable GPU Core for Real-Time Systems.

.- HLS4PC: A Parametrizable Framework For Accelerating Point-Based 3D Point Cloud Models on FPGA.

.- Hybrid unary-binary design for multiplier-less printed Machine Learning classifiers.

.- MT-TMVP: Modular Tiled TMVP-based Polynomial Multiplication for Post-Quantum Cryptography on FPGA s.

.- Deterministic Allocation and Scheduling for Buffered Exposed Datapath Architectures.

.- Exploiting temporal parallelism for LSTM Autoencoder acceleration on FPGA.

.- Exploring a Vector Processor Configuration Space for AI Workloads.

.- Application and Acceleration .

.- FlexiSAGA: A Flexible Systolic Array GEMM Accelerator for Sparse and Dense Processing.

.- SALSA: Sorting Acceleration Leveraging Smart Non-comparative Algorithms.

.- Mapping Virtual Brain Twins onto GroqChip.

.- Multipartner Research Projects .

.- TRISTAN & ISOLDE Chips-JU RISC-V Projects.

.- The EuroCCGreece HPC Competence Center.

.- Advanced Software Techniques for Resilience Against Error Upsets in Space.

.- Vitamin-V: Serverless Cloud Software Porting Progress.

.- The NEPHELE Meta-Orchestration Approach for Distributed Applications in the Computing Continuum.

.- REFMAP: From HPC to High Fidelity CFD Simulations to Optimized Flow Prediction Models for Next-Gen Urban Airspace Mobility.

.- AgRibot: Mutli-Cloud Computing Architecture for Smart and Sustainable Agriculture.

.- LLMs at the Edge: Hype or Hope? .

.- LLMs at the Edge: Hype or Hope?.

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