Principles of Secure Processor Architecture Design

Jakub Szefer's research interests are at the intersection of computer architecture and hardware security. Jakub's recent projects focus on security verification of processor architectures; hardware (FPGA) implementation of cryptographic algorithms, especially post-quantum cryptographic (PQC) algorithms; Cloud FPGA security; designs of new Physically Unclonable Functions (PUFs); and leveraging physical properties of computer hardware for new cryptographic and security applications. Jakub's research is currently supported through National Science Foundation and industry donations. Jakub is a recipient of a 2017 NSF CAREER award. In the summer of 2013, he became an Assistant Professor of Electrical Engineering at Yale University, where he started the Computer Architecture and Security Laboratory (CAS Lab). Prior to joining Yale, he received Ph.D. and M.A. degrees in Electrical Engineering from Princeton University, where he worked with his advisor, Prof. Ruby B. Lee, on secure processor architectures. He received a B.S. with highest honors in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign.

Margaret Martonosi is the Hugh Trumbull Adams '35 Professor of Computer Science at Princeton University, where she has been on the faculty since 1994. She is also currently serving a four-year term as Director of the Keller Center for Innovation in Engineering Education. Martonosi holds affiliated faculty appointments in Princeton EE, the Center for Information Technology Policy (CITP), the Andlinger Center for Energy and the Environment, and the Princeton Environmental Institute. She also holds an affiliated faculty appointment in Princeton EE. From 2005-2007, she served as Associate Dean for Academic Affairs for the Princeton University School of Engineering and Applied Science. In 2011, she served as Acting Director of Princeton's Center for Information Technology Policy (CITP). From August 2015 through March, 2017, she served as a Jefferson Science Fellow within the U.S. Department of State. Martonosi's research interests are in computer architecture and mobile computing, with particular focus on power-efficient systems. Her work has included the development of the Wattch power modeling tool and the Princeton ZebraNet mobile sensor network project for the design and real-world deployment of zebra tracking collars in Kenya. Her current research focuses on hardware-software interface approaches to manage heterogeneous parallelism and power-performance tradeoffs in systems ranging from smartphones to chip multiprocessors to large-scale data centers. Martonosi is a Fellow of both IEEE and ACM. Notable awards include the 2010 Princeton University Graduate Mentoring Award, the 2013 NCWIT Undergraduate Research Mentoring Award, the 2013 Anita Borg Institute Technical Leadership Award, the 2015 Marie Pistilli Women in EDA Achievement Award, the 2015 ISCA Long-Term Influential Paper Award, and the 2017 ACM SIGMOBILE Test-of-Time Award. In addition to many archival publications, Martonosi is an inventor on seven granted US patents, and has co-authored two technical reference books on power-aware computer architecture. She has served on the Board of Directors of the Computing Research Association (CRA), and will co-chair CRA-W from 2017-2020. Martonosi completed her Ph.D. at Stanford University, and also holds a Master's degree from Stanford and a bachelor's degree from Cornell University, all in Electrical Engineering.