
VHDL for Engineers
International Edition
Kenneth L. Short(Author)
Pearson (Publisher)
Published on 8. May 2008
Book
Mixed media product
720 pages
978-0-13-501810-1 (ISBN)
Article exhausted; check for reprint
Description
Suitable for use in a one- or two-semester course for computer and electrical engineering majors.
VHDL for Engineers, First Edition is perfect for anyone with a basic understanding of logic design and a minimal background in programming who desires to learn how to design digital systems using VHDL. No prior experience with VHDL is required. This text teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.
VHDL for Engineers, First Edition is perfect for anyone with a basic understanding of logic design and a minimal background in programming who desires to learn how to design digital systems using VHDL. No prior experience with VHDL is required. This text teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.
More details
Language
English
Place of publication
United States
Publishing group
Pearson Education (US)
Target group
Professional and scholarly
Dimensions
Height: 184 mm
Width: 235 mm
Thickness: 27 mm
Weight
1060 gr
ISBN-13
978-0-13-501810-1 (9780135018101)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
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Content
<b><P style="MARGIN: 0px" align=left text-align="left">Preface <i></i><P style="MARGIN: 0px" align=left text-align="left">1 Digital Design Using VHDL and PLDs <i>1</i><P style="MARGIN: 0px" align=left text-align="left">1.1 </b><P style="MARGIN: 0px" align=left text-align="left">VHDL/PLD Design Methodology <i>1</i><b><P style="MARGIN: 0px" align=left text-align="left">1.2 </b>Requirements Analysis and Specification <i>5</i><b><P style="MARGIN: 0px" align=left text-align="left">1.3 </b>VHDL Design Description <i>6</i><b><P style="MARGIN: 0px" align=left text-align="left">1.4 </b>Verification Using Simulation <i>11</i><b><P style="MARGIN: 0px" align=left text-align="left">1.5 </b>Testbenches <i>13</i><b><P style="MARGIN: 0px" align=left text-align="left">1.6 </b>Functional (Behavioral) Simulation <i>16</i><b><P style="MARGIN: 0px" align=left text-align="left">1.7 </b>Programmable Logic Devices (PLDs) <i>18</i><b><P style="MARGIN: 0px" align=left text-align="left">1.8 </b>SPLDs and the 22V10 <i>21</i><b><P style="MARGIN: 0px" align=left text-align="left">1.9 </b>Logic Synthesis for the Target PLD <i>27</i><b><P style="MARGIN: 0px" align=left text-align="left">1.10 </b>Place-and-Route and Timing Simulation <i>31</i><b><P style="MARGIN: 0px" align=left text-align="left">1.11 </b>Programming and Verifying a Target PLD <i>37</i><b><P style="MARGIN: 0px" align=left text-align="left">1.12 </b>VHDL/PLD Design Methodology Advantages <i>38</i><b><P style="MARGIN: 0px" align=left text-align="left">1.13 </b>VHDL's Development <i>39</i><b><P style="MARGIN: 0px" align=left text-align="left">1.14 </b>VHDL for Synthesis versus VHDL for Simulation <i>39</i><b><P style="MARGIN: 0px" align=left text-align="left">1.15 </b>This Book's Primary Objective <i>40</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><P style="MARGIN: 0px" align=left text-align="left"><b>2 Entities , Architectures , and Coding Styles <i>44</i><P style="MARGIN: 0px" align=left text-align="left">2.1 </b>Design Units, Library Units, and Design Entities <i>44</i><b><P style="MARGIN: 0px" align=left text-align="left">2.2 </b>Entity Declaration <i>45</i><b><P style="MARGIN: 0px" align=left text-align="left">2.3 </b>VHDL Syntax Definitions <i>47</i><b><P style="MARGIN: 0px" align=left text-align="left">2.4 </b>Port Modes <i>50</i><b><P style="MARGIN: 0px" align=left text-align="left">2.5 </b>Architecture Body <i>53</i><b><P style="MARGIN: 0px" align=left text-align="left">2.6 </b>Coding Styles <i>55</i><b><P style="MARGIN: 0px" align=left text-align="left">2.7 </b>Synthesis Results versus Coding Style <i>66</i><b><P style="MARGIN: 0px" align=left text-align="left">2.8 </b>Levels of Abstraction and Synthesis <i>69</i><b><P style="MARGIN: 0px" align=left text-align="left">2.9 </b>Design Hierarchy and Structural Style <i>71</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">3 Signals and Data Types <i>82</i><P style="MARGIN: 0px" align=left text-align="left">3.1 </b>Object Classes and Object Types <i>82</i><b><P style="MARGIN: 0px" align=left text-align="left">3.2 </b>Signal Objects <i>84</i><b><P style="MARGIN: 0px" align=left text-align="left">3.3 </b>Scalar Types <i>88</i><b><P style="MARGIN: 0px" align=left text-align="left">3.4 </b>Type Std_Logic <i>93</i><b><P style="MARGIN: 0px" align=left text-align="left">3.5 </b>Scalar Literals and Scalar Constants <i>99</i><b><P style="MARGIN: 0px" align=left text-align="left">3.6 </b>Composite Types <i>100</i><b><P style="MARGIN: 0px" align=left text-align="left">3.7 </b>Arrays <i>101</i><b><P style="MARGIN: 0px" align=left text-align="left">3.8 </b>Types Unsigned and Signed <i>107</i><b><P style="MARGIN: 0px" align=left text-align="left">3.9 </b>Composite Literals and Composite Constants <i>110</i><b><P style="MARGIN: 0px" align=left text-align="left">3.10 </b>Integer Types <i>112</i><b><P style="MARGIN: 0px" align=left text-align="left">3.11 </b>Port Types for Synthesis <i>116</i><b><P style="MARGIN: 0px" align=left text-align="left">3.12 </b>Operators and Expressions <i>118</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">4 Dataf low Style Combinational Design <i>123</i><P style="MARGIN: 0px" align=left text-align="left">4.1 </b>Logical Operators <i>123</i><b><P style="MARGIN: 0px" align=left text-align="left">4.2 </b>Signal Assignments in Dataflow Style Architectures <i>127</i><b><P style="MARGIN: 0px" align=left text-align="left">4.3 </b>Selected Signal Assignment <i>130</i><b><P style="MARGIN: 0px" align=left text-align="left">4.4 </b>Type Boolean and the Relational Operators <i>132</i><b><P style="MARGIN: 0px" align=left text-align="left">4.5 </b>Conditional Signal Assignment <i>134</i><b><P style="MARGIN: 0px" align=left text-align="left">4.6 </b>Priority Encoders <i>139</i><b><P style="MARGIN: 0px" align=left text-align="left">4.7 </b>Don't Care Inputs and Outputs <i>140</i><b><P style="MARGIN: 0px" align=left text-align="left">4.8 </b>Decoders <i>144</i><b><P style="MARGIN: 0px" align=left text-align="left">4.9 </b>Table Lookup <i>147</i><b><P style="MARGIN: 0px" align=left text-align="left">4.10 </b>Three-state Buffers <i>151</i><b><P style="MARGIN: 0px" align=left text-align="left">4.11 </b>Avoiding Combinational Loops <i>155</i><P style="MARGIN: 0px" align=left text-align="left"> <P style="MARGIN: 0px" align=left text-align="left"><b>5 Behavi oral Style Combinational Design <i>165</i><P style="MARGIN: 0px" align=left text-align="left">5.1 </b>Behavioral Style Architecture <i>165</i><b><P style="MARGIN: 0px" align=left text-align="left">5.2 </b>Process Statement <i>169</i><b><P style="MARGIN: 0px" align=left text-align="left">5.3 </b>Sequential Statements 170<b><P style="MARGIN: 0px" align=left text-align="left">5.4 </b>Case Statement <i>171</i><b><P style="MARGIN: 0px" align=left text-align="left">5.5 </b>If Statement <i>176</i><b><P style="MARGIN: 0px" align=left text-align="left">5.6 </b>Loop Statement <i>181</i><b><P style="MARGIN: 0px" align=left text-align="left">5.7 </b>Variables <i>185</i><b><P style="MARGIN: 0px" align=left text-align="left">5.8 </b>Parity Detector Example <i>188</i><b><P style="MARGIN: 0px" align=left text-align="left">5.9 </b>Synthesis of Processes Describing Combinational Systems <i>193</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">6 Event-Driven Simulation <i>201</i><P style="MARGIN: 0px" align=left text-align="left">6.1 </b>Simulator Approaches <i>201</i><b><P style="MARGIN: 0px" align=left text-align="left">6.2 </b>Elaboration <i>203</i><b><P style="MARGIN: 0px" align=left text-align="left">6.3 </b>Signal Drivers <i>208</i><b><P style="MARGIN: 0px" align=left text-align="left">6.4 </b>Simulator Kernel Process <i>210</i><b><P style="MARGIN: 0px" align=left text-align="left">6.5 </b>Simulation Initialization <i>212</i><b><P style="MARGIN: 0px" align=left text-align="left">6.6 </b>Simulation Cycles <i>215</i><b><P style="MARGIN: 0px" align=left text-align="left">6.7 </b>Signals versus Variables <i>223</i><b><P style="MARGIN: 0px" align=left text-align="left">6.8 </b>Delta Delays <i>230</i><b><P style="MARGIN: 0px" align=left text-align="left">6.9 </b>Delta Delays and Combinational Feedback <i>235</i><b><P style="MARGIN: 0px" align=left text-align="left">6.10 </b>Multiple Drivers <i>239</i><b><P style="MARGIN: 0px" align=left text-align="left">6.11 </b>Signal Attributes <i>241</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">7 Testbenche s for Combinational Designs <i>251</i><P style="MARGIN: 0px" align=left text-align="left">7.1 </b>Design Verification <i>251</i><b><P style="MARGIN: 0px" align=left text-align="left">7.2 </b>Functional Verification of Combinational Designs <i>255</i><b><P style="MARGIN: 0px" align=left text-align="left">7.3 </b>A Simple Testbench <i>255</i><b><P style="MARGIN: 0px" align=left text-align="left">7.4 </b>Physical Types <i>258</i><b><P style="MARGIN: 0px" align=left text-align="left">7.5 </b>Single Process Testbench <i>260</i><b><P style="MARGIN: 0px" align=left text-align="left">7.6 </b>Wait Statements <i>263</i><b><P style="MARGIN: 0px" align=left text-align="left">7.7 </b>Assertion and Report Statements <i>265</i><b><P style="MARGIN: 0px" align=left text-align="left">7.8 </b>Records and Table Lookup Testbenches <i>268</i><b><P style="MARGIN: 0px" align=left text-align="left">7.9 </b>Testbenches That Compute Stimulus and Expected Results <i>272</i><b><P style="MARGIN: 0px" align=left text-align="left">7.10 </b>Predefined Shift Operators <i>274</i><b><P style="MARGIN: 0px" align=left text-align="left">7.11 </b>Stimulus Order Based on UUT Functionality <i>276</i><b><P style="MARGIN: 0px" align=left text-align="left">7.12 </b>Comparing a UUT to a Behavioral Intent Model <i>279</i><b><P style="MARGIN: 0px" align=left text-align="left">7.13 </b>Code Coverage and Branch Coverage <i>281</i><b><P style="MARGIN: 0px" align=left text-align="left">7.14 </b>Post-Synthesis and Timing Verifications for Combinational<P style="MARGIN: 0px" align=left text-align="left">Designs <i>284</i><b><P style="MARGIN: 0px" align=left text-align="left">7.15 </b>Timing Models Using VITAL and SDF <i>288</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">8 Latches and Flip - flops <i>304</i><P style="MARGIN: 0px" align=left text-align="left">8.1 </b>Sequential Systems and Their Memory Elements <i>304</i><b><P style="MARGIN: 0px" align=left text-align="left">8.2 </b>D Latch <i>308</i><b><P style="MARGIN: 0px" align=left text-align="left">8.3 </b>Detecting Clock Edges <i>315</i><b><P style="MARGIN: 0px" align=left text-align="left">8.4 </b>D Flip-flops <i>317</i><b><P style="MARGIN: 0px" align=left text-align="left">8.5 </b>Enabled (Gated) Flip-flop <i>324</i><b><P style="MARGIN: 0px" align=left text-align="left">8.6 </b>Other Flip-flop Types <i>328</i><b><P style="MARGIN: 0px" align=left text-align="left">8.7 </b>PLD Primitive Memory Elements <i>331</i><b><P style="MARGIN: 0px" align=left text-align="left">8.8 </b>Timing Requirements and Synchronous Input Data <i>332</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">9 MultibitLatches, Registers, Counters,<P style="MARGIN: 0px" align=left text-align="left">and Memory <i>337</i><P style="MARGIN: 0px" align=left text-align="left">9.1 </b>Multibit Latches and Registers <i>337</i><b><P style="MARGIN: 0px" align=left text-align="left">9.2 </b>Shift Registers <i>340</i><b><P style="MARGIN: 0px" align=left text-align="left">9.3 </b>Shift Register Counters <i>346</i><b><P style="MARGIN: 0px" align=left text-align="left">9.4 </b>Counters <i>348</i><b><P style="MARGIN: 0px" align=left text-align="left">9.5 </b>Detecting Non-clock Signal Edges <i>360</i><b><P style="MARGIN: 0px" align=left text-align="left">9.6 </b>Microprocessor Compatible Pulse Width Modulated Signal<P style="MARGIN: 0px" align=left text-align="left">Generator <i>366</i><b><P style="MARGIN: 0px" align=left text-align="left">9.7 </b>Memories <i>370</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">10 Finite State Machines <i>380</i><P style="MARGIN: 0px" align=left text-align="left">10.1 </b>Finite State Machines <i>380</i><b><P style="MARGIN: 0px" align=left text-align="left">10.2 </b>FSM State Diagrams <i>386</i><b><P style="MARGIN: 0px" align=left text-align="left">10.3 </b>Three Process FSM VHDL Template <i>388</i><b><P style="MARGIN: 0px" align=left text-align="left">10.4 </b>State Diagram Development <i>392</i><b><P style="MARGIN: 0px" align=left text-align="left">10.5 </b>Decoder for an Optical Shaft Encoder <i>403</i><b><P style="MARGIN: 0px" align=left text-align="left">10.6 </b>State Encoding and State Assignment <i>409</i><b><P style="MARGIN: 0px" align=left text-align="left">10.7 </b>Supposedly Safe FSMs <i>414</i><b><P style="MARGIN: 0px" align=left text-align="left">10.8 </b>Inhibit Logic FSM Example <i>418</i><b><P style="MARGIN: 0px" align=left text-align="left">10.9 </b>Counters as Moore FSMs <i>422</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">11 ASM Charts and RTL Design <i>431</i><P style="MARGIN: 0px" align=left text-align="left">11.1 </b>Algorithmic State Machine Charts <i>431</i><b><P style="MARGIN: 0px" align=left text-align="left">11.2 </b>Converting ASM Charts to VHDL <i>43</i><b><P style="MARGIN: 0px" align=left text-align="left">11.3 </b>System Architecture <i>441</i><b><P style="MARGIN: 0px" align=left text-align="left">11.4 </b>Successive Approximation Register Design Example <i>445</i><b><P style="MARGIN: 0px" align=left text-align="left">11.5 </b>Sequential Multiplier Design <i>457</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">12 Subprograms <i>469</i><P style="MARGIN: 0px" align=left text-align="left">12.1 </b>Subprograms <i>469</i><b><P style="MARGIN: 0px" align=left text-align="left">12.2 </b>Functions <i>473</i><b><P style="MARGIN: 0px" align=left text-align="left">12.3 </b>Procedures <i>480</i><b><P style="MARGIN: 0px" align=left text-align="left">12.4 </b>Array Attributes and Unconstrained Arrays <i>484</i><b><P style="MARGIN: 0px" align=left text-align="left">12.5 </b>Overloading Subprograms and Operators <i>491</i><b><P style="MARGIN: 0px" align=left text-align="left">12.6 </b>Type Conversions <i>494</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">13 Packages <i>501</i><P style="MARGIN: 0px" align=left text-align="left">13.1 </b>Packages and Package Bodies <i>501</i><b><P style="MARGIN: 0px" align=left text-align="left">13.2 </b>Standard and De Facto Standard Packages <i>505</i><b><P style="MARGIN: 0px" align=left text-align="left">13.3 </b>Package STD_LOGIC_1164 <i>510</i><b><P style="MARGIN: 0px" align=left text-align="left">13.4 </b>Package NUMERIC_STD (IEEE Std 1076.3) <i>516</i><b><P style="MARGIN: 0px" align=left text-align="left">13.5 </b>Package STD_LOGIC_ARITH <i>523</i><b><P style="MARGIN: 0px" align=left text-align="left">13.6 </b>Packages for VHDL Text Output <i>524</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">14 Testbenches for Sequential Systems <i>526</i><P style="MARGIN: 0px" align=left text-align="left">14.1 </b>Simple Sequential Testbenches <i>526</i><b><P style="MARGIN: 0px" align=left text-align="left">14.2 </b>Generating a System Clock <i>527</i><b><P style="MARGIN: 0px" align=left text-align="left">14.3 </b>Generating the System Reset <i>531</i><b><P style="MARGIN: 0px" align=left text-align="left">14.4 </b>Synchronizing Stimulus Generation and Monitoring <i>532</i><b><P style="MARGIN: 0px" align=left text-align="left">14.5 </b>Testbench for Successive Approximation Register <i>538</i><b><P style="MARGIN: 0px" align=left text-align="left">14.6 </b>Determining a Testbench Stimulus for a Sequential System <i>542</i><b><P style="MARGIN: 0px" align=left text-align="left">14.7 </b>Using Procedures for Stimulus Generation <i>545</i><b><P style="MARGIN: 0px" align=left text-align="left">14.8 </b>Output Verification in Stimulus Procedures <i>550</i><b><P style="MARGIN: 0px" align=left text-align="left">14.9 </b>Bus Functional Models <i>552</i><b><P style="MARGIN: 0px" align=left text-align="left">14.10 </b>Response Monitors <i>560</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">15 Modular Design and Hierarchy <i>566</i><P style="MARGIN: 0px" align=left text-align="left">15.1 </b>Modular Design, Partitioning, and Hierarchy <i>566</i><b><P style="MARGIN: 0px" align=left text-align="left">15.2 </b>Design Units and Library Units <i>571</i><b><P style="MARGIN: 0px" align=left text-align="left">15.3 </b>Design Libraries <i>573</i><b><P style="MARGIN: 0px" align=left text-align="left">15.4 </b>Using Library Units <i>574</i><b><P style="MARGIN: 0px" align=left text-align="left">15.5 </b>Direct Design Entity Instantiation 577<b><P style="MARGIN: 0px" align=left text-align="left">15.6 </b>Components and Indirect Design Entity Instantiation <i>580</i><P style="MARGIN: 0px" align=left text-align="left"><b>15.7 </b>Configuration Declarations <i>587</i><b><P style="MARGIN: 0px" align=left text-align="left">15.8 </b>Component Connections <i>594</i><b><P style="MARGIN: 0px" align=left text-align="left">15.9 </b>Parameterized Design Entities <i>598</i><b><P style="MARGIN: 0px" align=left text-align="left">15.10 </b>Library of Parameterized Modules (LPM) <i>602</i><b><P style="MARGIN: 0px" align=left text-align="left">15.11 </b>Generate Statement <i>605</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">16 More Design Examples <i>615</i><P style="MARGIN: 0px" align=left text-align="left">16.1 </b>Microprocessor Compatible Quadrature<P style="MARGIN: 0px" align=left text-align="left">Decoder/Counter Design <i>615</i><b><P style="MARGIN: 0px" align=left text-align="left">16.2 </b>Verification of Quadrature Decoder/Counter <i>624</i><b><P style="MARGIN: 0px" align=left text-align="left">16.3 </b>Parameterized Quadrature Decoder/Counter <i>628</i><b><P style="MARGIN: 0px" align=left text-align="left">16.4 </b>Electronic Safe Design <i>630</i><b><P style="MARGIN: 0px" align=left text-align="left">16.5 </b>Verification of Electronic Safe <i>644</i><b><P style="MARGIN: 0px" align=left text-align="left">16.6 </b>Encoder for RF Transmitter Design <i>649</i><P style="MARGIN: 0px" align=left text-align="left"><i> </i><b><P style="MARGIN: 0px" align=left text-align="left">Appendix VHDL Attributes <i>659</i><P style="MARGIN: 0px" align=left text-align="left">Bibliography <i>663</i><P style="MARGIN: 0px" align=left text-align="left">Index</b>