Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs

Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have become imperative for the successful design of VLSI chips. This book presents the latest developments for modeling and analysis of VLSI systems in the presence of process variations at the nanometer scale. It focuses on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits.