
High-Level Synthesis Hardware Trojan Attacks and Countermeasures
Anirban Sengupta(Author)
Institution of Engineering and Technology (Publisher)
Published on 5. May 2026
Book
Hardback
242 pages
978-1-80705-067-2 (ISBN)
Description
Hardware trojans - which involve malicious modification of integrated circuits (ICs) during the design or fabrication stage - can give access to sensitive information, deny service, and so on. They can be difficult to detect but have serious consequences for the security of the IC.
Exploring hardware trojan attacks and their countermeasures using high level synthesis (HLS), this book covers different attack strategies, their detection and countermeasures, as well as future risks.
The expert author presents key information on hardware trojan attacks and their countermeasures. The book is split into four parts, starting with an introduction to hardware trojans and high-level synthesis, and then looking at various attack strategies. This is then followed by information on detection (a key issue in hardware trojan security), and countermeasures. The book finishes by looking at additional concerns and future directions of this key area in hardware security.
Readers will learn about topics such as hardware trojan classification and taxonomy, trojan attacks using malicious HLS framework, time bomb HLS-based hardware trojan attacks, trojan attacks on ML accelerator designs, other payloads of HLS trojan attack, trojan detection technique using DMR, and trojan detection and isolation technique and compromising IP designs via malicious exploitation of commercial CAD-HLS tools.
High-Level Synthesis Hardware Trojan Attacks and Countermeasures is a key resource for researchers and engineers working in hardware security and chip design.
Exploring hardware trojan attacks and their countermeasures using high level synthesis (HLS), this book covers different attack strategies, their detection and countermeasures, as well as future risks.
The expert author presents key information on hardware trojan attacks and their countermeasures. The book is split into four parts, starting with an introduction to hardware trojans and high-level synthesis, and then looking at various attack strategies. This is then followed by information on detection (a key issue in hardware trojan security), and countermeasures. The book finishes by looking at additional concerns and future directions of this key area in hardware security.
Readers will learn about topics such as hardware trojan classification and taxonomy, trojan attacks using malicious HLS framework, time bomb HLS-based hardware trojan attacks, trojan attacks on ML accelerator designs, other payloads of HLS trojan attack, trojan detection technique using DMR, and trojan detection and isolation technique and compromising IP designs via malicious exploitation of commercial CAD-HLS tools.
High-Level Synthesis Hardware Trojan Attacks and Countermeasures is a key resource for researchers and engineers working in hardware security and chip design.
More details
Series
Language
English
Place of publication
Stevenage
United Kingdom
Target group
College/higher education
Professional and scholarly
Product notice
sewn/stitched
Cloth over boards
Dimensions
Height: 234 mm
Width: 156 mm
Thickness: 14 mm
Weight
517 gr
ISBN-13
978-1-80705-067-2 (9781807050672)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Person
Anirban Sengupta is a full professor at the Indian Institute of Technology (IIT) Indore, India. He has more than 340 publications and patents, including 7 books, to his credit. He is a fellow of the IET, the British Computer Society, and IETE, and has been awarded the IEEE Chester Sall Memorial Consumer Electronics, IEEE Distinguished Visitor, and IEEE CESoc Outstanding Editor Award.
Author
Full ProfessorIndian Institute of Technology (IIT) Indore, Department of Computer Science and Engineering, India
Content
Part I: Foundations
Chapter 1: Introduction to hardware Trojans and high-level synthesis
Part II: Attack strategies
Chapter 2: Trojan attacks via malicious HLS framework
Chapter 3: Time-bomb HLS-based hardware Trojan attack for performance degradation
Chapter 4: Hardware Trojan attacks on HLS-based machine learning accelerators
Chapter 5: Power exhaustion attacks in HLS
Part III: Detection and countermeasures
Chapter 6: Machine learning-based detection of HLS Trojans
Chapter 7: HLS Trojan detection using Dual Modular Redundancy (DMR) techniques
Chapter 8: Trojan-resistant IP designs and isolation strategies
Part IV: Additional perspectives
Chapter 9: Compromising IP designs via malicious exploitation of commercial CAD-HLS tools vs. backdoor Trojan-inserted HLS frameworks
Chapter 10: Conclusion and future direction
Chapter 1: Introduction to hardware Trojans and high-level synthesis
Part II: Attack strategies
Chapter 2: Trojan attacks via malicious HLS framework
Chapter 3: Time-bomb HLS-based hardware Trojan attack for performance degradation
Chapter 4: Hardware Trojan attacks on HLS-based machine learning accelerators
Chapter 5: Power exhaustion attacks in HLS
Part III: Detection and countermeasures
Chapter 6: Machine learning-based detection of HLS Trojans
Chapter 7: HLS Trojan detection using Dual Modular Redundancy (DMR) techniques
Chapter 8: Trojan-resistant IP designs and isolation strategies
Part IV: Additional perspectives
Chapter 9: Compromising IP designs via malicious exploitation of commercial CAD-HLS tools vs. backdoor Trojan-inserted HLS frameworks
Chapter 10: Conclusion and future direction