Implementation aspects of binary and non-binary low-density parity-check decoders
1st Edition
Published in September 2017
Book
VII, 147 pages
978-3-95974-053-1 (ISBN)
Description
We live in the Information Era. In 2015 more than 1.4 billion smart phones have been
sold. Laptops, tablets and other mobile gadgets are permanent companions in our daily life.
This ongoing development requires ever increasing data rates in wireless communication.
Channel coding is a key technology to enable data rates of more than 100 Gbit/s in these
applications. Today, they are adopted in many communication standards, e.g. WiFi, LTE, or
WiMAX.
Forward error correction (FEC) schemes like low-density parity-check (LDPC) codes
achieve an excellent error correction performance close to the theoretical limit. However,
the iterative decoding algorithms are complex to implement in hardware, eventually leading
to expensive implementations. Especially in mobile devices the available resources (energy,
chip area etc.) for communication are strictly limited. Resolving this contradiction requires
innovative algorithms and architectures for LDPC decoding.
This thesis tackles issues in the design of binary and non-binary LDPC decoders. It
gives a comprehensive overview of the design space for both coding schemes. The most
critical challenges are identified and considered in use cases for optimized decoder design.
Design studies for an ultra high throughput decoder and an energy optimized decoder
proof the efficiency of the proposed architectures. Besides implementation efficiency, the
main goal of modern decoder architectures is to achieve the maximum error correction
performance. This thesis explores two orthogonal approaches to achieve the best possible
communication performance. On the one hand, algorithms for enhanced binary LDPC
decoding are presented. The new algorithm is integrated in state-of-the-art architecture
designs. On the other hand, a new processing scheme for the decoding of non-binary LDPC
codes is proposed. Non-binary LDPC codes have a better error correction performance than
their binary counter parts but suffer from a high computational complexity. An efficient
architecture for the optimized non-binary low-density parity-check (NB-LDPC) decoding
algorithm is explored.
sold. Laptops, tablets and other mobile gadgets are permanent companions in our daily life.
This ongoing development requires ever increasing data rates in wireless communication.
Channel coding is a key technology to enable data rates of more than 100 Gbit/s in these
applications. Today, they are adopted in many communication standards, e.g. WiFi, LTE, or
WiMAX.
Forward error correction (FEC) schemes like low-density parity-check (LDPC) codes
achieve an excellent error correction performance close to the theoretical limit. However,
the iterative decoding algorithms are complex to implement in hardware, eventually leading
to expensive implementations. Especially in mobile devices the available resources (energy,
chip area etc.) for communication are strictly limited. Resolving this contradiction requires
innovative algorithms and architectures for LDPC decoding.
This thesis tackles issues in the design of binary and non-binary LDPC decoders. It
gives a comprehensive overview of the design space for both coding schemes. The most
critical challenges are identified and considered in use cases for optimized decoder design.
Design studies for an ultra high throughput decoder and an energy optimized decoder
proof the efficiency of the proposed architectures. Besides implementation efficiency, the
main goal of modern decoder architectures is to achieve the maximum error correction
performance. This thesis explores two orthogonal approaches to achieve the best possible
communication performance. On the one hand, algorithms for enhanced binary LDPC
decoding are presented. The new algorithm is integrated in state-of-the-art architecture
designs. On the other hand, a new processing scheme for the decoding of non-binary LDPC
codes is proposed. Non-binary LDPC codes have a better error correction performance than
their binary counter parts but suffer from a high computational complexity. An efficient
architecture for the optimized non-binary low-density parity-check (NB-LDPC) decoding
algorithm is explored.