Introduction to VLSI Physical Design

Part 1 Introduction. Part 2 The top-down approach - location: partitioning; floor planning; placement; exercises; computer exercises. Part 3 The top-down approach - routing: fundamentals; global routing; detailed routing; routing in field-programmable gate-arrays; exercises; computer exercises. Part 4 Performance issues in circuit layout: interconnect delay model; timing driven placement; timing driven routing; via minimization; power minimization; discussion and other performance issues; exercises; computer exercises. Part 5 Single layer routing and applications: planar subset problem; single layer global routing; single layer detailed routing; wire-length and bend minimization techniques; over-the-cell routing; multi-chip modules; discussion; exercises; computer exercises. Part 6 Cell generation and programmable structures: programmable logic arrays; transistor chaining; gate matrix layout and Weinberger arrays; other CMOS cell layout generation techniques; CMOS cell layout styles considering performance issues; discussion; exercises; computer exercises. Part 7 Compaction: 1D compaction; 2D compaction; discussion; exercises; computer exercises.