Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems
Description
This book addresses the challenges associated with efficient Mixed-Criticality (MC) system design. We focus on application analysis through execution time analysis and task scheduling analysis in order to execute more low-criticality tasks in the system, i.e., improving the Quality-of-Service (QoS), while guaranteeing the correct execution of high-criticality tasks. Further, this book addresses the challenge of enhancing QoS using parallelism in multi-processor hardware platforms.
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Behnaz Ranjbar Received the PhD degree with Summa Cum Laude in Computer Science, from Technische Universität Dresden (TUD), Dresden, Germany, in 2022. Currently, she is a research associate at the Chair of Processor Design, TUD, Germany. Her current research interests include the design of embedded real-time systems, fault tolerance systems, and power-aware systems.
Alireza Ejlali received the PhD degree in computer engineering from Sharif University of Technology, Tehran, Iran, in 2006. He is currently an associate professor of computer engineering at SUT. From 2005 to 2006, he was a visiting researcher in the Electronic Systems Design Group, University of Southampton, Southampton, United Kingdom. He is currently the Director of the Embedded Sys- tems Research Laboratory, Department of Computer Engineering, Sharif University of Technology. His research interests include low power design, real-time, and fault-tolerant embedded systems.
Akash Kumar is a chaired Professor of Processor Design (with tenure) in the department of Computer Science at Technische Universität Dresden (TUD), Germany. From 2009 to 2015, he was with the Department of Electrical and Computer Engineering, NUS. He received the joint Ph.D. degree in electrical engineering in embedded systems from Eindhoven University of Technology (TU/e) and National University of Singapore (NUS), in 2009; joint Master's degree from TU/e and NUS in 2005 in embedded systems and Bachelor of Computer Engineering degree from NUS in 2002.
His research interests span various aspects of design automation in the context of embedded real-time systems with particular emphasis on reliable, resource-efficient and predictable architectures for embedded systems, including FPGA-based architectures. His research spans across various layers in the system design from hardware design to application analysis. He has published close to 250 articles in premier international conferences and journals in the areaof design automation. Together with his research group, he has released many open-source tool flows for system design and analysis to allow the community to reproduce their results and to further research in the related areas.
He has received Best Paper Award at DATA 2018, and best paper award nominations at DATE 2015, 2017 and 2020, FPL 2014, GLSVLSI 2014, ISVLSI 2020 and Supercomputing Conference 2015.
Content
Introduction.- Preliminaries and Literature Reviews.- Bounding Time in Mixed-Criticality Systems.- Safety- and Task-Drop-Aware Mixed-Criticality Task Scheduling.- Learning-Based Drop-Aware Mixed-Criticality Task Scheduling.- Fault-Tolerance and Power-Aware Multi-Core Mixed-Criticality System Design.- QoS- and Power-Aware Run-Time Scheduler for Multi-Core Mixed-Criticality Systems.- Conclusion.