Digital Hardware Testing
Transistor-level Fault Modeling and Testing
Published on 1. December 1992
Book
Hardback
340 pages
978-0-89006-580-8 (ISBN)
Description
Digital Hardware Testing presents realistic transistor-level fault models and testing methods for all types of circuits. The discussion details design-for-testability and built-in self-test methods, with coverage of boundary scan and emerging technologies such as partial scan, cross check, and circular self-test-path.
More details
Series
Language
English
Place of publication
Norwood
United States
Target group
College/higher education
Professional and scholarly
Product notice
Laminated cover
Illustrations
1, black & white illustrations
Dimensions
Height: 238 mm
Width: 159 mm
Thickness: 23 mm
Weight
635 gr
ISBN-13
978-0-89006-580-8 (9780890065808)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Content
Introduction to digital IC testing; faults in digital circuits; bridging faults in random logic; open faults in random logic; text generation and fault simulation; problems; testing of structured designs (programmable logic arrays); testing of random access memory; testing of sequential circuits; microprocessor testing; design for testability; current testing; reliability testing.