Arithmetic Built-In Self-Test for Embedded Systems
Published on 11. November 1997
Book
Hardback
288 pages
978-0-13-756438-5 (ISBN)
Description
This is a true cutting-edge circuit design from industry which may lead to corporate relationship with Mentor Graphics. It is a book for professionals which has some small usage as a grad level text. It clusters well with many recent and upcoming titles in the heart of my signing target area. The MS is camera-ready and the authors are adding more introductory and comprehensive material to broaden its market further.
More details
Language
English
Place of publication
Upper Saddle River
United States
Publishing group
Pearson Education (US)
Target group
College/higher education
Dimensions
Width: 232 mm
Thickness: 26 mm
Weight
641 gr
ISBN-13
978-0-13-756438-5 (9780137564385)
Copyright in bibliographic data is held by Nielsen Book Services Limited or its licensors: all rights reserved.
Schweitzer Classification
Content
1. Built-In Self-Test.
Introduction. Design for Testability. Generation of Test Vectors. Compaction of Test Responses. BIST Schemes for Random Logic. BIST for Memory Arrays.
2. Generation of Test Vectors.
Additive Generators of Exhaustive Patterns. Other Generation Schemes. Two-Dimensional Generators.
3. Test-Response Compaction.
Binary Adders. 1's Complement Adders. Rotate-Carry Adders. Cascaded Compaction Scheme.
4. Fault Diagnosis.
Analytical Model. Experimental Validation. The Quality of Diagnostic Resolution. Fault Diagnosis in Scan-Based Designs.
5. BIST of Data-Path Kernel.
Testing of ALU. Testing of the MAC Unit. Testing of the Microcontroller.
6. Fault Grading.
Fault Simulation Framework. Functional Fault Simulation. Experimental Results.
7. High-Level Synthesis.
Implementation-Dependent Fault Grading. Synthesis Steps. Simulation Results.
8. ABIST at Work.
Testing of Random Logic. Memory Testing. Digital Integrators. Leaking Integrators.
9. Epilog.
Bibliography.
A. Tables of Generators.
B. Assembly Language.
Index.
Introduction. Design for Testability. Generation of Test Vectors. Compaction of Test Responses. BIST Schemes for Random Logic. BIST for Memory Arrays.
2. Generation of Test Vectors.
Additive Generators of Exhaustive Patterns. Other Generation Schemes. Two-Dimensional Generators.
3. Test-Response Compaction.
Binary Adders. 1's Complement Adders. Rotate-Carry Adders. Cascaded Compaction Scheme.
4. Fault Diagnosis.
Analytical Model. Experimental Validation. The Quality of Diagnostic Resolution. Fault Diagnosis in Scan-Based Designs.
5. BIST of Data-Path Kernel.
Testing of ALU. Testing of the MAC Unit. Testing of the Microcontroller.
6. Fault Grading.
Fault Simulation Framework. Functional Fault Simulation. Experimental Results.
7. High-Level Synthesis.
Implementation-Dependent Fault Grading. Synthesis Steps. Simulation Results.
8. ABIST at Work.
Testing of Random Logic. Memory Testing. Digital Integrators. Leaking Integrators.
9. Epilog.
Bibliography.
A. Tables of Generators.
B. Assembly Language.
Index.