VHDL Made Easy!

Preface.


What This Book Is. Who Can Use This Book. Coding Styles. The Companion CD-ROM. Acknowledgments.



1. Introduction.


Goals of This Book. What Is VHDL? A Brief History of VHDL. How Is VHDL Used? The FPGA/ASIC Design Process. When Should You Use VHDL? When Should You Not Use VHDL? What About Verilog? What About PLD Languages?



2. A First Look At VHDL.


Simple Example: A Comparator. Comparator Source File. Entities and Architectures. Entity Declaration. Architecture Declaration And Body. Data Types. Design Units. Structure Of A Small Design. More Typical Design Description. Levels of Abstraction (Styles). Sample Circuit. Comparator. Shifter (Entity). Concurrent and Sequential VHDL. Signals and Variables. Using a Procedure to Describe Registers. Using a Component to Describe Registers. Structural VHDL. Test Benches. Sample Test Bench. What We've Learned So Far.



3. Exploring Objects and Data Types.


Signals. Variables. Constants. Literals. Types and Subtypes. Scalar Types. Composite Types. Operators. Attributes. Type Conversions and Type Marks. Resolved and Unresolved Types.



4. Using Standard Logic.


IEEE Standard 1164. Advantages of IEEE 1164. Using The Standard Logic Package. Std_logic_vector and Std_ulogic_vector. Type Conversion and Standard Logic. Standard Logic Data Types. Standard Logic Operators. Standard Logic Type Conversion Functions. Strength Stripping Functions. Edge Detection Functions. Miscellaneous Checking Functions. Standard 1076.3 (the Numeric Standard). Using Numeric Data Types. Numeric Standard Types: Unsigned and Signed. Numeric Standard Operators. Numeric Array Resize Functions. Numeric Type Conversion Functions.



5. Understanding Concurrent Statements.


The Concurrent Area. Concurrent Signal Assignments. Conditional Signal Assignment. Selected Signal Assignment. Conditional vs. Selected Assignment. Procedure Calls. Generate Statements. Concurrent Processes. Component Instantiations. Delay Specifications. Signal Drivers.



6. Understanding Sequential Statements.


The Process Statement. Using Processes for Combinational Logic. Using Processes for Registered Logic. Using Processes for State Machines. Specifying State Machine Encodings. Using Processes for Test Stimulus. Sequential Statements in Subprograms. Signal and Variable Assignments. If- Then-Else Statements. Case Statements. Loops. Loop Termination.



7. Creating Modular Designs.


Functions and Procedures. Functions. Procedures. Parameter Types. Mapping of Parameters.



8. Partitioning Your Design.


Blocks. Guarded Blocks. Packages. Package Bodies. Design Libraries. Package Visibility. Components. Mapping of Ports. Generics. Configurations.



9. Writing Test Benches.


A Simple Test Bench. Using Assert Statements. Using Loops and Multiple Processes. Writing Test Vectors. Reading and Writing Files with Text I/O. Reading Non-tabular Data from Files. Creating a Test Language. You're On Your Way...



Appendix A: Getting The Most Out Of Synthesis.


Appendix B: A VITAL Primer.


Appendix C: Using VHDL Simulation.


Introduction. Design Management. Simulation Features. Understanding Simulation. Loading the Sample Project. Using the Hierarchy Browser. Compiling Modules for Simulation. Linking Modules for Simulation. Using the Accolade Simulator. Summary.



Appendix D: Test Bench Generation from Timing Diagrams.


Introduction. Background: What is a Test Bench? Automating Test Bench Generation. Tutorial: Generating Test Benches with The WaveFormer.



Appendix E: VHDL Keyword List.


Appendix F: Driving Game Listings.


Appendix G: Synopsys Textio Package.


Appendix H: Glossary.


Appendix I: Other Resources.


Index.