Guidebook for Managing Silicon Chip Reliability
1st Edition
Published on 7. October 2019
Book
Paperback/Softback
224 pages
978-0-367-40006-4 (ISBN)
Description
Achieving cost-effective performance over time requires an organized, disciplined, and time-phased approach to product design, development, qualification, manufacture, and in-service management. Guidebook for Managing Silicon Chip Reliability examines the principal failure mechanisms associated with modern integrated circuits and describes common practices used to resolve them.
This quick reference on semiconductor reliability addresses the key question: How will the understanding of failure mechanisms affect the future?
Chapters discuss:
failure sites, operational loads, and failure mechanism
intrinsic device sensitivities
electromigration
hot carrier aging
time dependent dielectric breakdown
mechanical stress induced migration
alpha particle sensitivity
electrostatic discharge (ESD) and electrical overstress
latch-up
qualification
screening
guidelines for designing reliability
Guidebook for Managing Silicon Chip Reliability focuses on device failure and causes throughout - providing a thorough framework on how to model the mechanism, test for defects, and avoid and manage damage. It will serve as an exceptional resource for electrical engineers as well as mechanical engineers working in the field of electronic packaging.
This quick reference on semiconductor reliability addresses the key question: How will the understanding of failure mechanisms affect the future?
Chapters discuss:
failure sites, operational loads, and failure mechanism
intrinsic device sensitivities
electromigration
hot carrier aging
time dependent dielectric breakdown
mechanical stress induced migration
alpha particle sensitivity
electrostatic discharge (ESD) and electrical overstress
latch-up
qualification
screening
guidelines for designing reliability
Guidebook for Managing Silicon Chip Reliability focuses on device failure and causes throughout - providing a thorough framework on how to model the mechanism, test for defects, and avoid and manage damage. It will serve as an exceptional resource for electrical engineers as well as mechanical engineers working in the field of electronic packaging.
More details
Language
English
Place of publication
London
United Kingdom
Publishing group
Taylor & Francis Ltd
Target group
Professional and scholarly
Professional Practice & Development
Dimensions
Height: 234 mm
Width: 156 mm
Thickness: 12 mm
Weight
351 gr
ISBN-13
978-0-367-40006-4 (9780367400064)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
Michael Pecht | Riko Radojcic | Gopal Rao
Guidebook for Managing Silicon Chip Reliability
E-Book
11/2017
CRC Press
€54.99
Available for download
Michael Pecht | Riko Radojcic | Gopal Rao
Guidebook for Managing Silicon Chip Reliability
E-Book
11/2017
CRC Press
€55.49
Available for download
Michael G. Pecht
Guidebook for Managing Silicon Chip Reliability
Book
12/1998
1st Edition
CRC Press
€156.60
Shipment within 15-20 days
Persons
Pecht, Michael; Radojcic, Riko; Rao, Gopal
Content
Introduction How Devices Fail Intrinsic Mechanisms Extrinsic Mechanisms Intrinsic Device Sensitivities Device Transconductance Sensitivities Leakage Current Sensitivities Breakdown Issues Electromigration Description of the Mechanism Modeling of the Mechanism How to Detect/Test How to Manage Hot Carrier Aging Description of the Mechanism Modeling of the Mechanism Detection of Hot Carrier Aging Avoidance of Hot Carrier Aging Time Dependent Dielectric Breakdown Description of the Mechanism Modeling of the Mechanism How to Detect/Test How to Avoid and Manage Mechanical Stress Induced Migration Description of the Mechanism Modeling of the Mechanism How to Detect/Test How to Manage Alpha Particle Sensitivity Description of the Mechanism Modeling of the Mechanism Prevention of Alpha Particle Induced Damage Electrostatic Discharge and Electrical Overstress Description of the Mechanism Modeling of the Mechanism Avoiding ESD/EOS Failures Latch-Up Description of the Mechanism How to Detect How to Avoid Qualification Qualification Testing Virtual Qualification Screening Functional Tests Burn-In Tests Iddq Tests Design for Reliability Design System Effective Management of Wear-Out Failures Extrinsic Reliability Mechanisms Infant Mortality Failure Mechanisms Circuit Sensitivities Summary