
An Introduction to RISC V. "Reduced Instruction Set Computer" Processor
Arpita Patel(Author)
GRIN Verlag
1st Edition
Published on 17. May 2024
Book
Paperback/Softback
38 pages
978-3-389-02842-1 (ISBN)
Description
Document from the year 2024 in the subject Computer Science, grade: A, , language: English, abstract: RISC-V, an open-source Instruction Set Architecture (ISA), has become a significant performer in the realm of computer architecture, challenging traditional proprietary designs and opening the doors for innovation and customization. Initially in this work, RISC-V¿s historical evolution, its architecture, including its design concepts, instruction set, register file and implementations, were understood through a literature survey.A comprehensive literature survey is conducted on various variants of RISC-V family and their applications, which include lowering total costs, speeding up processor execution, consuming less power, and creating a more manageable and compact versions of the original architecture. The study includes a thorough analysis of several RISC-V variations. According to review of the literature, the 32-bit biRISC-V processor core is the newest member of the RISC-V family and using superscalar dual issue design to increase processor overall throughput.
More details
Edition
1. Auflage
Language
English
Product notice
Paperback (trade)
Unsewn / adhesive bound
Dimensions
Height: 210 mm
Width: 148 mm
Thickness: 4 mm
Weight
68 gr
ISBN-13
978-3-389-02842-1 (9783389028421)
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Schweitzer Classification