Cross-Layer Reliability of Computing Systems
Published on 22. October 2020
Book
Hardback
328 pages
978-1-78561-797-3 (ISBN)
Description
Reliability has always been a major concern in designing computing systems. However, the increasing complexity of such systems has led to a situation where efforts for assuring reliability have become extremely costly, both for the design of solutions for the mitigation of possible faults, and for the reliability assessment of such techniques.
Cross-layer reliability is fast becoming the preferred solution. In a cross-layer resilient system, physical and circuit level techniques can mitigate low-level faults. Hardware redundancy can be used to manage errors at the hardware architecture layer. Eventually, software implemented error detection and correction mechanisms can manage those errors that escaped the lower layers of the stack.
This book presents state-of-the-art solutions for increasing the resilience of computing systems, both at single levels of abstraction and multi-layers. The book begins by addressing design techniques to improve the resilience of computing systems, covering the logic layer, the architectural layer and the software layer. The second part of the book focuses on cross-layer resilience, including coverage of physical stress, reliability assessment approaches, fault injection at the ISA level, analytical modelling for cross-later resiliency, and stochastic methods.
Cross-Layer Reliability of Computing Systems is a valuable resource for researchers, postgraduate students and professional computer architects focusing on the dependability of computing systems.
Cross-layer reliability is fast becoming the preferred solution. In a cross-layer resilient system, physical and circuit level techniques can mitigate low-level faults. Hardware redundancy can be used to manage errors at the hardware architecture layer. Eventually, software implemented error detection and correction mechanisms can manage those errors that escaped the lower layers of the stack.
This book presents state-of-the-art solutions for increasing the resilience of computing systems, both at single levels of abstraction and multi-layers. The book begins by addressing design techniques to improve the resilience of computing systems, covering the logic layer, the architectural layer and the software layer. The second part of the book focuses on cross-layer resilience, including coverage of physical stress, reliability assessment approaches, fault injection at the ISA level, analytical modelling for cross-later resiliency, and stochastic methods.
Cross-Layer Reliability of Computing Systems is a valuable resource for researchers, postgraduate students and professional computer architects focusing on the dependability of computing systems.
More details
Series
Language
English
Place of publication
Stevenage
United Kingdom
Target group
College/higher education
Professional and scholarly
Product notice
sewn/stitched
Cloth over boards
Dimensions
Height: 239 mm
Width: 160 mm
Thickness: 20 mm
Weight
703 gr
ISBN-13
978-1-78561-797-3 (9781785617973)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Persons
Giorgio Di Natale is director of research for the National Research Center of France at the TIMA laboratory in Grenoble, France. His research interests include hardware security and trust, reliability, fault tolerance, and testing. He is the chair of the TTTC (Computer Society), Golden Core member of the Computer Society and Senior member of the IEEE.
Dimitris Gizopoulos is a professor in the Department of Informatics & Telecommunications at the National and Kapodistrian University of Athens, Greece, where he leads the Computer Architecture Laboratory. His research focuses on the dependability, performance and energy efficiency of computing systems architectures built around general purpose microprocessors and specialized accelerators. He is a Fellow of IEEE and a Senior Member of ACM.
Stefano Di Carlo is a tenured associate professor at Politecnico di Torino, Italy. His research interests include DFT, BIST, and dependability. He has published more than 170 papers in peer reviewed IEEE and ACM journals and conferences.
Alberto Bosio is a full professor at Ecole Centrale de Lyon - INL in France. His research interests include approximate computing, in-memory computing, test and diagnosis of digital circuits and systems and reliability.
Ramon Canal is an associate professor and the vice dean of postgraduate studies at the Facultat d'Informatica de Barcelona at the Universitat Politecnica de Catalunya-Barcelona Tech (UPC). He is currently working in the Computer Architecture Department in the VirtuOS (Virtualization and Operating Systems) group.
Dimitris Gizopoulos is a professor in the Department of Informatics & Telecommunications at the National and Kapodistrian University of Athens, Greece, where he leads the Computer Architecture Laboratory. His research focuses on the dependability, performance and energy efficiency of computing systems architectures built around general purpose microprocessors and specialized accelerators. He is a Fellow of IEEE and a Senior Member of ACM.
Stefano Di Carlo is a tenured associate professor at Politecnico di Torino, Italy. His research interests include DFT, BIST, and dependability. He has published more than 170 papers in peer reviewed IEEE and ACM journals and conferences.
Alberto Bosio is a full professor at Ecole Centrale de Lyon - INL in France. His research interests include approximate computing, in-memory computing, test and diagnosis of digital circuits and systems and reliability.
Ramon Canal is an associate professor and the vice dean of postgraduate studies at the Facultat d'Informatica de Barcelona at the Universitat Politecnica de Catalunya-Barcelona Tech (UPC). He is currently working in the Computer Architecture Department in the VirtuOS (Virtualization and Operating Systems) group.
Editor
Director of ResearchNational Research Center of France, TIMA Laboratory, Grenoble, France
ProfessorNational and Kapodistrian University of Athens, Department of Informatics & Telecommunications, Greece
Tenured Associate ProfessorPolitecnico di Torino, Italy
Full ProfessorEcole Centrale de Lyon - INL, France
Associate ProfessorUniversitat Politecnica de Catalunya-Barcelona Tech (UPC), Facultat d'Informatica de Barcelona, Catalonia, Spain
Content
Part I: Design techniques to improve the resilience of computing systems
Chapter 1: Technological layer
Chapter 2: Design techniques to improve the resilience of computing systems: logic layer
Chapter 3: Design techniques to improve the resilience of computing systems: architectural layer
Chapter 4: Design techniques to improve the resilience of computing systems: software layer
Chapter 5: Cross-layer resilience
Part II: Reliability assessment
Chapter 6: Physical stress
Chapter 7: Soft error modeling and simulation
Chapter 8: Microarchitecture-level reliability assessment of multi-core processors
Chapter 9: Fault injection at the instruction set architecture (ISA) level
Chapter 10: Analytical modeling for crosslayer resiliency
Chapter 11: Stochastic methods
Chapter 1: Technological layer
Chapter 2: Design techniques to improve the resilience of computing systems: logic layer
Chapter 3: Design techniques to improve the resilience of computing systems: architectural layer
Chapter 4: Design techniques to improve the resilience of computing systems: software layer
Chapter 5: Cross-layer resilience
Part II: Reliability assessment
Chapter 6: Physical stress
Chapter 7: Soft error modeling and simulation
Chapter 8: Microarchitecture-level reliability assessment of multi-core processors
Chapter 9: Fault injection at the instruction set architecture (ISA) level
Chapter 10: Analytical modeling for crosslayer resiliency
Chapter 11: Stochastic methods