VLSI Architecture for Signal, Speech, and Image Processing
Advances, Challenges, and Potential
1st Edition
Published on 3. November 2022
Book
Hardback
320 pages
978-1-77463-730-2 (ISBN)
Description
This new volume introduces various VLSI (very-large-scale integration) architecture for DSP filters, speech filters, and image filters, detailing their key applications and discussing different aspects and technologies used in VLSI design, models and architectures, and more. The volume explores the major challenges with the aim to develop real-time hardware architecture designs that are compact and accurate. It provides useful research in the field of computer arithmetic and can be applied for various arithmetic circuits, for their digital implementation schemes, and for performance considerations.
More details
Language
English
Place of publication
Oakville
Canada
Target group
College/higher education
Professional and scholarly
Academic and Postgraduate
Illustrations
45 s/w Tabellen, 168 s/w Zeichnungen, 174 s/w Abbildungen, 6 s/w Photographien bzw. Rasterbilder
45 Tables, black and white; 168 Line drawings, black and white; 6 Halftones, black and white; 174 Illustrations, black and white
Dimensions
Height: 240 mm
Width: 161 mm
Thickness: 23 mm
Weight
678 gr
ISBN-13
978-1-77463-730-2 (9781774637302)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
Durgesh Nandan | Basant Kumar Mohanty | Sanjeev Kumar
VLSI Architecture for Signal, Speech, and Image Processing
E-Book
11/2022
1st Edition
Apple Academic Press Inc.
€194.99
Available for download
Durgesh Nandan | Basant Kumar Mohanty | Sanjeev Kumar
VLSI Architecture for Signal, Speech, and Image Processing
E-Book
11/2022
1st Edition
Apple Academic Press Inc.
€194.99
Available for download
Persons
Durgesh Nandan, PhD, is a Research Mentor and Account Manager at Accendere Knowledge Management Services Pvt. Ltd. He formerly served as Head of the Department of Electronics and Communication Engineering, IASSCOM Fortune Institutes of Technology, India. He is a session chair, technical program committee chair, reviewer, and member of more than 50 national and international conferences. He is the author or a co-author of more than 90 papers and the author/co-author of two books.
Basant Kumar Mohanty, PhD, is Professor and Associate Dean (Research) at the Mukesh Patel School of Technology, Management and Engineering at the Narsee Moonjee Institute of Management Studies, Mumbai, India. He is also an Associate Editor for the Journal of Circuits, Systems, and Signal Processing and a senior member of IEEE Circuits and System Society. He has published over 60 technical papers and conference proceedings and has collaborated on research with faculties of top technical universities.
Sanjeev Kumar, PhD, is a Research Mentor at CL Educate Ltd., India. He was formerly affiliated with TIT Group of Institutes, India, and the Oriental Group of Institutes, Bhopal, India. He was also a project fellow at the Division of MMIC in the Defence Research and Development Organisation, Delhi, India. He acts as technical program chair, reviewer, and member of more than 40 refereed national/international conferences. He is the author or a co-author of more than 65 papers in international journals and conference proceedings.
Rajeev Kumar Arya, PhD, is Assistant Professor of Electronics and Communication Engineering at the National Institute of Technology, Patna, India. He was formerly affiliated with CMR Engineering College, Hyderabad, India. He serves as a guest editor of the International Journal of Information Technology and Web Engineering and the International Journal of Computational Systems Engineering and is a reviewer for IEEE Communication Letter and other journals.
Basant Kumar Mohanty, PhD, is Professor and Associate Dean (Research) at the Mukesh Patel School of Technology, Management and Engineering at the Narsee Moonjee Institute of Management Studies, Mumbai, India. He is also an Associate Editor for the Journal of Circuits, Systems, and Signal Processing and a senior member of IEEE Circuits and System Society. He has published over 60 technical papers and conference proceedings and has collaborated on research with faculties of top technical universities.
Sanjeev Kumar, PhD, is a Research Mentor at CL Educate Ltd., India. He was formerly affiliated with TIT Group of Institutes, India, and the Oriental Group of Institutes, Bhopal, India. He was also a project fellow at the Division of MMIC in the Defence Research and Development Organisation, Delhi, India. He acts as technical program chair, reviewer, and member of more than 40 refereed national/international conferences. He is the author or a co-author of more than 65 papers in international journals and conference proceedings.
Rajeev Kumar Arya, PhD, is Assistant Professor of Electronics and Communication Engineering at the National Institute of Technology, Patna, India. He was formerly affiliated with CMR Engineering College, Hyderabad, India. He serves as a guest editor of the International Journal of Information Technology and Web Engineering and the International Journal of Computational Systems Engineering and is a reviewer for IEEE Communication Letter and other journals.
Content
1. Evolution of 1-D, 2-D, and 3-D Lifting Discrete Wavelet Transform VLSI Architecture 2. Execution of Lifting-Scheme Discrete Wavelet Transform by Canonical Signed Digit Multiplier 3. Radix-8 Booth Multiplier in Terms of Power and Area Efficient for Application in the Field of 2D DWT Architecture 4. Design and Performance Evaluation of Energy Efficient 8-Bit ALU at Ultra Low Supply Voltages Using FinFET with 20nm Technology 5. Design and Statistical Analysis of Strong Arbiter PUFs for Device Authentication and Identification 6. An Impact of Aging on Arbiter Physical Unclonable Functions 7. Advanced Power Management Methodology for SoCs Using UPF 8. Architecture Design: Network-on-Chip 9. Routing Strategy: Network-on-Chip Architectures 10. Self-Driven Clock Gating Technique for Dynamic Power Reduction of High-Speed Complex Systems 11. Optimization of SOC Sub-Circuits Using Mathematical Modeling 12. An Efficient Design of D Flip Flop in Quantum-Dot Cellular Automata (QCA) for Sequential Circuits 13. Design and Performance Analysis of Digitally Controlled DC-DC Converter