Nano-CMOS and Post-CMOS Electronics: Volume 1
Devices and modelling
Published on 12. April 2016
Book
Hardback
384 pages
978-1-84919-997-1 (ISBN)
Description
The demand for ever smaller and portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nanodevices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOS devices) are emerging that could replace the traditional and ubiquitous silicon transistor. This book explores these nanoelectronics at the device level including modelling and design.
Topics covered include high-k dielectrics; high mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays; anodic metal-insulator-metal (MIM) capacitors; graphene transistors; junction and doping free transistors; nanoscale gigh-k/metal-gate CMOS and FinFET based logic libraries; multiple-independent-gate nanowire transistors; carbon nanotubes for efficient power delivery; timing driven buffer insertion for carbon nanotube interconnects; memristor modeling; and neuromorphic devices and circuits.
This book is essential reading for researchers, research-focused industry designers/developers, and advanced students working on next-generation electronic devices and circuits.
Topics covered include high-k dielectrics; high mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays; anodic metal-insulator-metal (MIM) capacitors; graphene transistors; junction and doping free transistors; nanoscale gigh-k/metal-gate CMOS and FinFET based logic libraries; multiple-independent-gate nanowire transistors; carbon nanotubes for efficient power delivery; timing driven buffer insertion for carbon nanotube interconnects; memristor modeling; and neuromorphic devices and circuits.
This book is essential reading for researchers, research-focused industry designers/developers, and advanced students working on next-generation electronic devices and circuits.
More details
Series
Language
English
Place of publication
Stevenage
United Kingdom
Target group
College/higher education
Professional and scholarly
Product notice
sewn/stitched
Cloth over boards
Dimensions
Height: 241 mm
Width: 160 mm
Thickness: 25 mm
Weight
680 gr
ISBN-13
978-1-84919-997-1 (9781849199971)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Persons
Saraju Mohanty is Professor at the Department of Computer Science and Engineering, University of North Texas, where he is the director of NanoSystem Design Laboratory (NSDL). His research interests focus on Energy-Efficient High-Performance Secure Electronic Systems. Prof. Mohanty is an inventor of 4 US patents, and an author of 200 peer-reviewed articles and 3 books. Prof. Mohanty is the current Chair of Technical Committee on Very Large Scale Integration (TCVLSI) of the IEEE Computer Society, is on the editorial board of IET Circuits, Devices and Systems, Integration and Journal of Low Power Electronics, and serves on the organizing and program committee of several international conferences.
Ashok Srivastava is Professor of Engineering at the Division of Electrical & Computer Engineering of Louisiana State University, Baton Rouge, where his research interests lie in low-power VLSI design and testability for nanoscale transistors and integration, and nanoelectronics with focus on novel emerging devices and integrated circuit design based on carbon nanotubes, graphene and other reduced dimension 2D materials. He is the author of more than 160 technical papers including conference proceedings, book chapters, a patent and a book on Carbon Based Electronics. Prof. Srivastava serves on the Editorial Review Board of Modeling and Numerical Simulation of Material Science (MNSMS), Journal of Material Science and Chemical Engineering (JMSCE), The Scientific World Journal (Electronics) and is Editor-in-Chief of the Journal of Sensor Technology.
Ashok Srivastava is Professor of Engineering at the Division of Electrical & Computer Engineering of Louisiana State University, Baton Rouge, where his research interests lie in low-power VLSI design and testability for nanoscale transistors and integration, and nanoelectronics with focus on novel emerging devices and integrated circuit design based on carbon nanotubes, graphene and other reduced dimension 2D materials. He is the author of more than 160 technical papers including conference proceedings, book chapters, a patent and a book on Carbon Based Electronics. Prof. Srivastava serves on the Editorial Review Board of Modeling and Numerical Simulation of Material Science (MNSMS), Journal of Material Science and Chemical Engineering (JMSCE), The Scientific World Journal (Electronics) and is Editor-in-Chief of the Journal of Sensor Technology.
Content
Chapter 1: High-? dielectrics and device reliability
Chapter 2: High mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays
Chapter 3: Anodic metal-insulator-metal (MIM) capacitors
Chapter 4: Graphene transistors - present and beyond
Chapter 5: Junction and doping-free transistors for future computing
Chapter 6: Nanoscale high-?/metal-gate CMOS and FinFET based logic libraries
Chapter 7: FinFET and reliability considerations of next-generation processors
Chapter 8: Multiple-independent-gate nanowire transistors: from technology to advanced SoC design
Chapter 9: Exploration of carbon nanotubes for efficient power delivery
Chapter 10: Timing driven buffer insertion for carbon nanotube interconnects
Chapter 11: Memristor modeling - static, statistical, and stochastic methodologies
Chapter 12: Neuromorphic devices and circuits
Chapter 2: High mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays
Chapter 3: Anodic metal-insulator-metal (MIM) capacitors
Chapter 4: Graphene transistors - present and beyond
Chapter 5: Junction and doping-free transistors for future computing
Chapter 6: Nanoscale high-?/metal-gate CMOS and FinFET based logic libraries
Chapter 7: FinFET and reliability considerations of next-generation processors
Chapter 8: Multiple-independent-gate nanowire transistors: from technology to advanced SoC design
Chapter 9: Exploration of carbon nanotubes for efficient power delivery
Chapter 10: Timing driven buffer insertion for carbon nanotube interconnects
Chapter 11: Memristor modeling - static, statistical, and stochastic methodologies
Chapter 12: Neuromorphic devices and circuits