Functional Verification of Programmable Embedded Architectures
A Top-Down Approach
Published on 4. December 2014
Book
Paperback/Softback
XIX, 180 pages
978-1-4899-7336-8 (ISBN)
Description
It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification. Functional errors manifest themselves very early in the design flow, and unless they are detected up front, they can result in severe consequence- both financially and from a safety viewpoint. Indeed, several recent instances of high-profile functional errors (e. g. , the Pentium FDIV bug) have resulted in - creased attention paid to verifying the functional correctness of designs. Recent efforts have proposed augmenting the traditional RTL simulation-based validation methodology with formal techniques in an attempt to uncover hard-to-find c- ner cases, with the goal of trying to reach RTL functional verification closure. However, what is often not highlighted is the fact that in spite of the tremendous time and effort put into such efforts at the RTL and lower levels of abstraction, the complexity of contemporary embedded systems makes it difficult to guarantee functional correctness at the system level under all possible operational scenarios. The problem is exacerbated in current System-on-Chip (SOC) design meth- ologies that employ Intellectual Property (IP) blocks composed of processor cores, coprocessors, and memory subsystems. Functional verification becomes one of the major bottlenecks in the design of such systems.
More details
Edition
2005 ed.
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Research
Illustrations
XIX, 180 p.
Dimensions
Height: 235 mm
Width: 155 mm
Thickness: 12 mm
Weight
312 gr
ISBN-13
978-1-4899-7336-8 (9781489973368)
DOI
10.1007/b137514
Schweitzer Classification
Other editions
Additional editions
Prabhat Mishra | Nikil D. Dutt
Functional Verification of Programmable Embedded Architectures
A Top-Down Approach
E-Book
12/2005
1st Edition
Springer
€96.29
Available for download
Prabhat Mishra | Nikil D. Dutt
Functional Verification of Programmable Embedded Architectures
A Top-Down Approach
Book
07/2005
Springer
€106.99
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Persons
WeixunWang is a software engineer in Amazon.com, Seattle,WA. He received his B.E. degree in software engineering from the Software Institute, Nanjing University, China, in 2007, and a Ph.D. degree in computer engineering from the University of Florida in 2011. His research interests include energy-aware computing, design automation of embedded systems, computer architecture, reconfigurable architectures and real-time scheduling. He has published more than 10 papers in these fields. He is a member of IEEE.
Prabhat Mishra is an Associate Professor in the Department of Computer and Information Science and Engineering (CISE) at the University of Florida. His research interests include design automation of embedded systems, hardware/software verification, VLSI CAD, and low-power reconfigurable architectures. He received his B.E. from Jadavpur University, Kolkata, in 1994, M.Tech. from the Indian Institute of Technology, Kharagpur in 1996, and Ph.D. from the University of California, Irvine, in 2004 - all in Computer Science. Prior to joining University of Florida, he spent several years in various semiconductor and design automation companies, including Intel, Motorola, Synopsys and Texas Instruments. He has published two books (Springer 2005 and MK 2008), nine book chapters and more than 80 research articles in premier journals and conferences. His research has been recognized by several awards including the NSF CAREER Award from the National Science Foundation, two best paper awards (VLSI Design 2011 and CODES+ISSS 2003), several best paper award nominations, and 2004 EDAA Outstanding Dissertation Award from the European Design Automation Association. He has also received the 2007 International Educator of the Year Award from the UF College of Engineering for his significant international research and teaching contributions. He currently serves as an Associate Editor of IEEE Design & Test of Computers (D&T), Guest Editor of IEEE Transactionson Computers (TC), the Information Director of ACM Transactions on Design Automation of Electronic Systems (TODAES), and as a program/organizing committee member of several ACM and IEEE conferences including ICCAD, DATE, ASPDAC, CODES+ISSS, and VLSI Design. He has also served as General Chair of IEEE High Level Design Validation and Test (HLDVT) 2010, Program Chair of HLDVT 2009, and Guest Editor of IEEE Design & Test of Computers (D&T), Journal of Electronic Testing (JETTA) and International Journal of Parallel Programming (IJPP). He is a senior member of ACM and a senior member of IEEE.
Sanjay Ranka is a Professor in the Department of Computer Information Science and Engineering at University of Florida. His current research interests are energy efficient computing, high performance computing, data mining and informatics. Most recently he was the Chief Technology Officer at Paramark where he developed real-time optimization software for optimizing marketing campaigns. Sanjay has also held positions as a tenured faculty member at Syracuse University and as a researcher/visitor at IBM T.J. Watson Research Labs and Hitachi America Limited. Sanjay earned his Ph.D. (Computer Science) from the University of Minnesota and a B. Tech. in Computer Science from IIT, Kanpur, India. He has coauthored two books: Elements of Neural Networks (MIT Press) and Hypercube Algorithm (Springer Verlag), 75 journal articles and 125 refereed conference articles. His recent work has received a student best paper award at ACM-BCB 2010, best paper runner up award at KDD-2009, a nomination for the Robbins Prize for the best paper in journal of Physics in Medicine and Biology for 2008, and a best paper award at ICN 2007. He is a fellow of the IEEE and AAAS and a member of IFIP Committee on System Modeling and Optimization. He is the associate Editor-in-Chief of the Journal of Parallel and Distributed Computing and an associate editor for IEEE Transactions onParallel and Distributed Computing, IEEE Transac
Content
to Functional Verification.- Architecture Specification.- Architecture Specification.- Validation of Specification.- Top-Down Validation.- Executable Model Generation.- Design Validation.- Functional Test Generation.- Future Directions.- Conclusions.