PCI-X System Architecture
Published on 12. December 2000
Book
Paperback/Softback
752 pages
978-0-201-72682-4 (ISBN)
Description
The PCI-X bus will start appearing in advanced PCs within months, delivering breakthrough performance, transfer rates of up to 1.06 Gb/sec, and backward compatibility with the PCI standard. Now, there's a comprehensive guide to PCI-X, covering everything engineers and developers need to create robust, reliable PCI-X boards and software. As with all MindShare books, PCI-X System Architecture is written in an accessible, tutorial style proven to train engineers. It's based on MindShare's leading edge PCI-X course, and reflects extensive feedback and insights from hundreds of working professionals. The book presents detailed descriptions of every aspect of the PCI-X specification, including: device types and bus initialization, error detection and handling, split completion messages, and 64-bit transactions. It offers in-depth coverage of device enumeration and configuration; traffic analysis and load tuning, PCI-X bridges, electrical issues, and much more. For all computer hardware and software design engineers, and for all developers concerned with advanced PC hardware.
More details
Language
English
Place of publication
Boston
United States
Publishing group
Pearson Education (US)
Target group
College/higher education
Dimensions
Height: 233 mm
Width: 187 mm
Thickness: 33 mm
Weight
1120 gr
ISBN-13
978-0-201-72682-4 (9780201726824)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Persons
MindShare, Inc. is one of the leading technical training companies in the hardware industry, providing innovative courses for dozens of companies, including Intel, IBM, and Compaq.
Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.
Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.
Content
About This Book.
I. BASIC CONCEPTS.
1. PCI Needed Improvement.
2. PCI-X Improves on PCI.
3. Bus Protocol/Speed = Lowest Common Denominator.
4. Device Types and Bus Initialization.
5. PCI-X Is a Registered Bus.
6. Intro to Commands.
7. Intro to Transaction Phases.
8. Intro to Transaction Termination.
9. Intro to Split and Immediate Transactions.
II. TRANSACTION PROTOCOL.
10. Bus Arbitration.
11. Detailed Command Description.
12. Latency Rules.
13. The Address, Attribute, and Response Phases.
14. Dword Transactions.
15. Burst Transactions.
16. Transaction Terminations.
17. Split Completion Messages.
18. 64-Bit Transactions.
19. Parity Generation and Checking
III. DEVICE CONFIGURATION.
20. Configuration Transactions.
21. Non-Bridge Configuration Registers.
22. Bridge Configuration Registers
IV. LOAD TUNING.
23. Load Tuning Mechanisms
V. PCI-X BRIDGES.
24. PCIX-to-PCIX Bridges.
25. Locked Transaction Series
VI. ERROR DETECTION AND HANDLING.
26. Error Detection and Handling
VII. ELECTRICAL ISSUES.
27. Electrical Issues.
Appendix A: Protocol Rules.
Appendix B: Glossary.
Index.
I. BASIC CONCEPTS.
1. PCI Needed Improvement.
2. PCI-X Improves on PCI.
3. Bus Protocol/Speed = Lowest Common Denominator.
4. Device Types and Bus Initialization.
5. PCI-X Is a Registered Bus.
6. Intro to Commands.
7. Intro to Transaction Phases.
8. Intro to Transaction Termination.
9. Intro to Split and Immediate Transactions.
II. TRANSACTION PROTOCOL.
10. Bus Arbitration.
11. Detailed Command Description.
12. Latency Rules.
13. The Address, Attribute, and Response Phases.
14. Dword Transactions.
15. Burst Transactions.
16. Transaction Terminations.
17. Split Completion Messages.
18. 64-Bit Transactions.
19. Parity Generation and Checking
III. DEVICE CONFIGURATION.
20. Configuration Transactions.
21. Non-Bridge Configuration Registers.
22. Bridge Configuration Registers
IV. LOAD TUNING.
23. Load Tuning Mechanisms
V. PCI-X BRIDGES.
24. PCIX-to-PCIX Bridges.
25. Locked Transaction Series
VI. ERROR DETECTION AND HANDLING.
26. Error Detection and Handling
VII. ELECTRICAL ISSUES.
27. Electrical Issues.
Appendix A: Protocol Rules.
Appendix B: Glossary.
Index.