AGP System Architecture
Published on 17. February 1999
Book
Paperback/Softback
272 pages
978-0-201-37964-8 (ISBN)
Description
Second Edition now available! The Accelerated Graphics Port (AGP) interface is a new platform bus specification that enables high performance graphics capabilities-especially 3-D and video-over networks and on individual PCs. Platform independent, AGP is supported by numerous hardware and software vendors, and is now standard on Pentium II computers. Software and hardware engineers working with graphics must have a good understanding of this important technology. AGP System Architecture provides an overview of the technology, a detailed description of the specification, and a practical tutorial for mastering AGP. Comprehensive and concise, it presents all the information you need to understand and utilize this proliferating technology. In particular, this book focuses on 3-D graphics and video-related issues-the applications most served by AGP. You will find coverage of the following essential topics.
*AGP advantages over PCI graphics for rendering 3-D images *AGP signaling requirements, including electrical AC and DC specifications and AGP driver and receiver characteristics *Signals for AGP-compliant masters and targets *AGP arbitration, with a look at optimization of grant pipelining *AGP transaction requests and ordering rules *AGP and Fast Write transactions in the 1X, 2X, and 4X data transfer modes *AGP hardware environment, including add-in cards, connectors, and the motherboard *AGP-specific configuration registers This indispensable resource will enable you to utilize AGP tools, design a high quality AGP device and support AGP in software applications. The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title is designed to illustrate the relationship between the software and hardware, and thoroughly explains the architecture, features, and operation of systems built using one particular type of chip or hardware specification. 0201379643B04062001
*AGP advantages over PCI graphics for rendering 3-D images *AGP signaling requirements, including electrical AC and DC specifications and AGP driver and receiver characteristics *Signals for AGP-compliant masters and targets *AGP arbitration, with a look at optimization of grant pipelining *AGP transaction requests and ordering rules *AGP and Fast Write transactions in the 1X, 2X, and 4X data transfer modes *AGP hardware environment, including add-in cards, connectors, and the motherboard *AGP-specific configuration registers This indispensable resource will enable you to utilize AGP tools, design a high quality AGP device and support AGP in software applications. The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title is designed to illustrate the relationship between the software and hardware, and thoroughly explains the architecture, features, and operation of systems built using one particular type of chip or hardware specification. 0201379643B04062001
More details
Language
English
Place of publication
Boston
United States
Publishing group
Pearson Education (US)
Target group
College/higher education
Dimensions
Height: 233 mm
Width: 185 mm
Thickness: 13 mm
Weight
465 gr
ISBN-13
978-0-201-37964-8 (9780201379648)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
New editions
MindShare, Inc. | Dave Dzatko | Tom Shanley
AGP System Architecture
Book
11/1999
2nd Edition
Addison Wesley
€50.75
Article is exhausted; no reprint
Persons
MindShare, Inc. is one of the leading technical training companies in the hardware industry, providing innovative courses for dozens of companies, including Intel, IBM, and Compaq.
David Dzatko has over ten years of experience designing and testing computer systems. He is currently an instructor with MindShare, Inc., teaching computer architecture to leading companies in the computer industry.
0201379643AB07142003
David Dzatko has over ten years of experience designing and testing computer systems. He is currently an instructor with MindShare, Inc., teaching computer architecture to leading companies in the computer industry.
0201379643AB07142003
Content
Acknowledgements.
About This Book.
The MindShare Architecture Series.
Cautionary Note.
Organization of This Book.
Who This Book Is For.
Prerequisite Knowledge.
Documentation Conventions.
Hexadecimal Notation.
Binary Notation.
Decimal Notation.
Bits versus Byte Notation.
Identification of Bit Fields (logical groups of bits or signals).
Visit Our Web Site.
We Want Your Feedback.
1. The Need for AGP.
Introduction to the 3-D Graphics Pipeline.
Geometry Calculations.
Rendering Calculations.
Texture Mapping.
Processing of Texture Maps with PCI Graphics.
How Much Local Memory is Dedicated to Textures?
How Much Texture Data for a Given Application?
Local Frame Buffer is Not Large Enough.
DMA Texturing.
PCI Bus Limitations.
Summary.
2. The AGP Solution.
Motivation for AGP.
AGP Revision 2.0 Features.
Dynamic Memory Allocation.
High Bandwidth Data Transfer Modes.
Core Logic = Target, AGP Accelerator = Master.
Bus Structure Similar to PCI.
Dedicated Interface for Graphics.
Transaction Pipelining.
PCI Configuration Mechanism.
Grant Pipelining.
AGP Connector vs. PCI Connector.
Optional Fast Write Transaction.
Sideband Addressing.
AGP Texturing: the "Execute" Model.
Snoops of Texture Accesses Can Be Eliminated.
Elimination of Texture Storage in Accelerator's Local Memory.
Textures Ideal Candidate to Move to Main Memory.
Performance Enhancements Relative to PCI DMA.
AGP Memory Allocation.
Core Logic Requirements.
Cache Coherency Requirements.
PCI Bus Master Writes to the AGP Master.
AGP Remapping Support for PCI Bus Masters.
Monochrome Device Adapter (MDA) Support.
AGP Transaction Queuing Models.
Decoupled Requests and Data.
PCI Transaction Enqueuing on AGP.
Performance Considerations.
PCI Read Transactions.
AGP Read Transactions.
Guaranteed Latency.
Typical Latency.
Mean Bandwidth.
Number of Devices.
Enqueuing Requests and Delivering Data in 1X Mode.
Drawing Convention Used.
Enqueuing Multiple Requests Using AD and C/BE Busses.
Back-to-Back Read Data Transactions.
3. The Signaling Environment.
AGP Voltage Characteristics.
DC Specifications.
3.3 Volt Signaling.
1.5 Volt Signaling.
Incremental Requirements for 2X and 4X Mode Operation.
1X Transfer Mode Timing Model.
Critical 1X Mode Timings.
Clocks.
Outputs.
Inputs.
Reset.
2X and 4X Transfer Mode Timing Model.
Definition of the Outer Loop.
Definition of the Inner Loop.
Strobe/Data Relationship in 2X Mode.
Strobe/Data Relationship in 4X Mode.
Using Strobes as Differential Signal Pairs in 4X Mode.
Four Time Domains.
Driver Characteristics.
Receiver Characteristics.
Changes to Clock Frequencies in Mobile Designs.
4. The Signal Groups.
The Required and Optional Signals for AGP Masters.
The Required and Optional Signals for AGP Targets.
Description of Signals.
Address/Data and Command.
AGP Requests.
Interface and Flow Control.
Arbitration and Status.
AGP Clock, Data Strobes and Request Strobes.
System.
USB.
Power Management.
Special.
Error Reporting.
PCI Signals Not Supported.
Signal Types.
5. AGP Arbitration.
Introduction to the AGP Arbiter.
Master Needs to Issue Transaction Request.
Target Needs to Initiate a Data Transfer.
GNT# and the Status Bus (ST[2::0]).
AGP Master's Request Signal.
When the Core Logic Must Start a Data Transfer.
GNT# Pipelining 94
6. AGP Commands and Ordering Rules.
Command Types and the Transfer Length.
Read Commands and Transfer Length.
Write Commands.
Dual-Address Cycle.
Flush and Fence Commands.
Reserved Commands.
AGP Ordering Rules.
Relationship of AGP and CPU or PCI Transactions.
Relationship of High- and Low-Priority AGP Transaction Streams.
Relationship of Same Priority AGP Streams (Reads and Writes).
Fence Command.
Flush Command.
What's the Problem?
PCI-Based Graphics Accelerator Solution.
AGP-Based Graphics Accelerator Solution.
7. AGP Request Transactions.
Two Request Enqueuing Mechanisms.
Enqueuing Transaction Requests via AD and C/BE Busses.
Example Request Enqueued Using AD and C/BE Busses.
64-Bit Memory Addressing.
Multiple Requests Being Enqueued Using 64-Bit Addressing.
Enqueuing Transaction Requests via the Sideband Address Port.
Four SBA Command Types.
Sideband Address Port Operation.
Example.
SBA Idle Time.
SBA Data Transfer Modes.
Sideband Strobe Synchronization Protocol.
AGP Request Transaction Flow Control.
8. AGP versus PCI Transactions.
Decoupled versus Coupled Data Transactions.
PCI Flow Control.
AGP Data Flow Control.
General.
Three Times Where Data Can Be Delayed.
AGP Master Flow Control.
AGP Target Flow Control.
Use of the RBF# Signal.
9. 1X, 2X, and 4X Data Transactions.
Introduction.
1X Transfer Mode Data Transactions.
Multiple Data Block Read Transaction.
Multiple Block Read Data Transaction with Wait States.
Read Data Transaction, Delay Prior to First Block.
Write Data Transaction, Minimum Delay.
Back-to-Back Write Data Transactions, No Delays.
2X Transfer Mode Data Transactions.
Back-to-Back Read Data Transactions, No Delays.
Multiple Block Read, No Delays.
Multiple Block Write with Wait States.
Back-to-Back Write Data Transactions, Minimum Delay.
Maximum Shift between Generation of Ready & Arrival of Strobes at Receiver.
Minimum Shift between Generation of Ready & Arrival of Strobes at Receiver.
4X Transfer Mode Data Transactions.
Back-to-Back Read Data Transactions, No Delay.
Multiple Block Read, No Delays.
Multiple Block Read with Delayed Second Data Block.
Back-to-Back Write Data Transactions, No Delay.
10. Fast Write Transactions.
Introduction to the Fast Write Transaction.
Write Transactions in 1X Mode.
Fast Write Transactions in 2X Mode.
Fast Write in 2X Mode, No Delays.
Fast Write in 2X Mode, Wait States Added.
Fast Write Transactions in 4X Mode.
Target-Initiated Premature Transaction Termination.
Retry.
Disconnect.
Master-Initiated Premature Transaction Termination.
Back-to-Back Fast Write Transactions.
Fast Back-to-Back, Fast Write Transactions.
Use of the WBF# Signal.
Short, Fast Write Transactions and DEVSEL#.
11. The Physical Environment.
Point-to-Point Topology.
Signal Routing and Layout.
Trace Impedance and Line Termination.
Add-In Card Clock Skew Specifications.
Vref Generation.
For 3.3V AGP in 2X Data Transfer Mode.
For 1.5V AGP in 2X and 4X Data Transfer Modes.
Component Pinout Recommendations 228
Motherboard/Add-in Card Interoperability.
Pull-Up/Pull-Down Resistors.
Maximum AC Ratings and Device Protection.
Power Supply.
Mechanicals.
AGP Pro.
Connector Pinout.
12. AGP Configuration.
System Configuration and AGP Device Initialization.
BIOS Initialization Requirements.
Operating System Initialization Requirements.
Capabilities List.
AGP Status Register.
AGP Command Register.
Microsoft DirectDraw.
Multifunction AGP Devices.
Index. 0201379643T04062001
About This Book.
The MindShare Architecture Series.
Cautionary Note.
Organization of This Book.
Who This Book Is For.
Prerequisite Knowledge.
Documentation Conventions.
Hexadecimal Notation.
Binary Notation.
Decimal Notation.
Bits versus Byte Notation.
Identification of Bit Fields (logical groups of bits or signals).
Visit Our Web Site.
We Want Your Feedback.
1. The Need for AGP.
Introduction to the 3-D Graphics Pipeline.
Geometry Calculations.
Rendering Calculations.
Texture Mapping.
Processing of Texture Maps with PCI Graphics.
How Much Local Memory is Dedicated to Textures?
How Much Texture Data for a Given Application?
Local Frame Buffer is Not Large Enough.
DMA Texturing.
PCI Bus Limitations.
Summary.
2. The AGP Solution.
Motivation for AGP.
AGP Revision 2.0 Features.
Dynamic Memory Allocation.
High Bandwidth Data Transfer Modes.
Core Logic = Target, AGP Accelerator = Master.
Bus Structure Similar to PCI.
Dedicated Interface for Graphics.
Transaction Pipelining.
PCI Configuration Mechanism.
Grant Pipelining.
AGP Connector vs. PCI Connector.
Optional Fast Write Transaction.
Sideband Addressing.
AGP Texturing: the "Execute" Model.
Snoops of Texture Accesses Can Be Eliminated.
Elimination of Texture Storage in Accelerator's Local Memory.
Textures Ideal Candidate to Move to Main Memory.
Performance Enhancements Relative to PCI DMA.
AGP Memory Allocation.
Core Logic Requirements.
Cache Coherency Requirements.
PCI Bus Master Writes to the AGP Master.
AGP Remapping Support for PCI Bus Masters.
Monochrome Device Adapter (MDA) Support.
AGP Transaction Queuing Models.
Decoupled Requests and Data.
PCI Transaction Enqueuing on AGP.
Performance Considerations.
PCI Read Transactions.
AGP Read Transactions.
Guaranteed Latency.
Typical Latency.
Mean Bandwidth.
Number of Devices.
Enqueuing Requests and Delivering Data in 1X Mode.
Drawing Convention Used.
Enqueuing Multiple Requests Using AD and C/BE Busses.
Back-to-Back Read Data Transactions.
3. The Signaling Environment.
AGP Voltage Characteristics.
DC Specifications.
3.3 Volt Signaling.
1.5 Volt Signaling.
Incremental Requirements for 2X and 4X Mode Operation.
1X Transfer Mode Timing Model.
Critical 1X Mode Timings.
Clocks.
Outputs.
Inputs.
Reset.
2X and 4X Transfer Mode Timing Model.
Definition of the Outer Loop.
Definition of the Inner Loop.
Strobe/Data Relationship in 2X Mode.
Strobe/Data Relationship in 4X Mode.
Using Strobes as Differential Signal Pairs in 4X Mode.
Four Time Domains.
Driver Characteristics.
Receiver Characteristics.
Changes to Clock Frequencies in Mobile Designs.
4. The Signal Groups.
The Required and Optional Signals for AGP Masters.
The Required and Optional Signals for AGP Targets.
Description of Signals.
Address/Data and Command.
AGP Requests.
Interface and Flow Control.
Arbitration and Status.
AGP Clock, Data Strobes and Request Strobes.
System.
USB.
Power Management.
Special.
Error Reporting.
PCI Signals Not Supported.
Signal Types.
5. AGP Arbitration.
Introduction to the AGP Arbiter.
Master Needs to Issue Transaction Request.
Target Needs to Initiate a Data Transfer.
GNT# and the Status Bus (ST[2::0]).
AGP Master's Request Signal.
When the Core Logic Must Start a Data Transfer.
GNT# Pipelining 94
6. AGP Commands and Ordering Rules.
Command Types and the Transfer Length.
Read Commands and Transfer Length.
Write Commands.
Dual-Address Cycle.
Flush and Fence Commands.
Reserved Commands.
AGP Ordering Rules.
Relationship of AGP and CPU or PCI Transactions.
Relationship of High- and Low-Priority AGP Transaction Streams.
Relationship of Same Priority AGP Streams (Reads and Writes).
Fence Command.
Flush Command.
What's the Problem?
PCI-Based Graphics Accelerator Solution.
AGP-Based Graphics Accelerator Solution.
7. AGP Request Transactions.
Two Request Enqueuing Mechanisms.
Enqueuing Transaction Requests via AD and C/BE Busses.
Example Request Enqueued Using AD and C/BE Busses.
64-Bit Memory Addressing.
Multiple Requests Being Enqueued Using 64-Bit Addressing.
Enqueuing Transaction Requests via the Sideband Address Port.
Four SBA Command Types.
Sideband Address Port Operation.
Example.
SBA Idle Time.
SBA Data Transfer Modes.
Sideband Strobe Synchronization Protocol.
AGP Request Transaction Flow Control.
8. AGP versus PCI Transactions.
Decoupled versus Coupled Data Transactions.
PCI Flow Control.
AGP Data Flow Control.
General.
Three Times Where Data Can Be Delayed.
AGP Master Flow Control.
AGP Target Flow Control.
Use of the RBF# Signal.
9. 1X, 2X, and 4X Data Transactions.
Introduction.
1X Transfer Mode Data Transactions.
Multiple Data Block Read Transaction.
Multiple Block Read Data Transaction with Wait States.
Read Data Transaction, Delay Prior to First Block.
Write Data Transaction, Minimum Delay.
Back-to-Back Write Data Transactions, No Delays.
2X Transfer Mode Data Transactions.
Back-to-Back Read Data Transactions, No Delays.
Multiple Block Read, No Delays.
Multiple Block Write with Wait States.
Back-to-Back Write Data Transactions, Minimum Delay.
Maximum Shift between Generation of Ready & Arrival of Strobes at Receiver.
Minimum Shift between Generation of Ready & Arrival of Strobes at Receiver.
4X Transfer Mode Data Transactions.
Back-to-Back Read Data Transactions, No Delay.
Multiple Block Read, No Delays.
Multiple Block Read with Delayed Second Data Block.
Back-to-Back Write Data Transactions, No Delay.
10. Fast Write Transactions.
Introduction to the Fast Write Transaction.
Write Transactions in 1X Mode.
Fast Write Transactions in 2X Mode.
Fast Write in 2X Mode, No Delays.
Fast Write in 2X Mode, Wait States Added.
Fast Write Transactions in 4X Mode.
Target-Initiated Premature Transaction Termination.
Retry.
Disconnect.
Master-Initiated Premature Transaction Termination.
Back-to-Back Fast Write Transactions.
Fast Back-to-Back, Fast Write Transactions.
Use of the WBF# Signal.
Short, Fast Write Transactions and DEVSEL#.
11. The Physical Environment.
Point-to-Point Topology.
Signal Routing and Layout.
Trace Impedance and Line Termination.
Add-In Card Clock Skew Specifications.
Vref Generation.
For 3.3V AGP in 2X Data Transfer Mode.
For 1.5V AGP in 2X and 4X Data Transfer Modes.
Component Pinout Recommendations 228
Motherboard/Add-in Card Interoperability.
Pull-Up/Pull-Down Resistors.
Maximum AC Ratings and Device Protection.
Power Supply.
Mechanicals.
AGP Pro.
Connector Pinout.
12. AGP Configuration.
System Configuration and AGP Device Initialization.
BIOS Initialization Requirements.
Operating System Initialization Requirements.
Capabilities List.
AGP Status Register.
AGP Command Register.
Microsoft DirectDraw.
Multifunction AGP Devices.
Index. 0201379643T04062001