Integrating Functional and Temporal Domains in Logic Design
The False Path Problem and Its Implications
Published on 31. May 1991
Book
Hardback
XXIII, 212 pages
978-0-7923-9163-0 (ISBN)
Description
This book is an extension of one author's doctoral thesis on the false path problem. The work was begun with the idea of systematizing the various solutions to the false path problem that had been proposed in the literature, with a view to determining the computational expense of each versus the gain in accuracy. However, it became clear that some of the proposed approaches in the literature were wrong in that they under estimated the critical delay of some circuits under reasonable conditions. Further, some other approaches were vague and so of questionable accu racy. The focus of the research therefore shifted to establishing a theory (the viability theory) and algorithms which could be guaranteed correct, and then using this theory to justify (or not) existing approaches. Our quest was successful enough to justify presenting the full details in a book. After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by separating the tempo ral and logical (or functional) behaviour of combinational circuits. This separation is the fruit of several unstated assumptions; first, that one can ignore the logical relationships of wires in a network when considering timing behaviour, and, second, that one can ignore timing considerations when attempting to discover the values of wires in a circuit.
More details
Series
Edition
1991 ed.
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Research
Product notice
sewn/stitched
Cloth over boards
Illustrations
XXIII, 212 p.
Dimensions
Height: 241 mm
Width: 160 mm
Thickness: 18 mm
Weight
535 gr
ISBN-13
978-0-7923-9163-0 (9780792391630)
DOI
10.1007/978-1-4615-3960-5
Schweitzer Classification
Other editions
Additional editions
Patrick C. McGeer | Robert K. Brayton
Integrating Functional and Temporal Domains in Logic Design
The False Path Problem and Its Implications
Book
09/2012
Springer
€106.50
Shipment within 7-9 days
Content
1 Introduction.- 1.1 Timing Analysis of Circuits.- 1.2 The General False Path Problem.- 1.3 A Note on Notation.- 1.4 Logic Notation.- 1.5 Outline.- 2 The False Path Problem.- 2.1 Introduction.- 2.2 Dynamic Timing Analysis.- 2.3 Viable Paths.- 2.4 Symmetric Networks and Monotonicity.- 2.5 Viability Under Network Transformations.- 2.6 The Viability Function.- 2.7 Summary.- 3 False Path Detection Algorithms.- 3.1 Generic False Path Detection Algorithm.- 3.2 Viability Analysis Procedure.- 3.3 Dynamic Programming Algorithm Example.- 3.4 Finding all the Longest Viable Paths.- 3.5 Recent Work.- 4 System Considerations and Approximations.- 4.1 Approximation Theory and Practice.- 4.2 "Weak" Viability.- 4.3 The Brand-Iyengar Procedure.- 4.4 The Du-Yen-Ghanta Criteria.- 4.5 The Chen-Du Criterion.- 4.6 More Macroexpansion Transformations.- 4.7 Biased Satisfiability Tests.- 4.8 Axes of Approximation.- 4.9 The Lllama Timing Environment.- 4.10 Experimental Results.- 5 Hazard Prevention in Combinational Circuits.- 5.1 Introduction.- 5.2 Hazards.- 5.3 The Boolean n-Space.- 5.4 The SDC Set and Restricted Cubes.- 5.5 Ordering The Inputs.- 6 Timing Analysis in Hazard-Free Networks.- 6.1 Introduction.- 6.2 Robustness of Dynamic Sensitization.- 6.3 The Dynamic Sensitization Function.- 6.4 Algorithms.- 6.5 Conclusion.- A Complexity Results.- A.1 An Introduction to Polynomial Reducibility.- B A Family of Operators.- C Fast Procedures for Computing Dataflow Sets.- C.1 Introduction.- C.2 Terminology.- C.3 The New Approach.- C.4 Computations.- C.4.1 Basic Algorithms.- C.4.2 Transitivity.- C.4.4 Evaluation Algorithms.- C.5 Correctness.- C.6 Complexity Analysis.- C.7 Efficiency.- C.8 Sparse Matrix Implementation.- C.9 An Improvement.- C.10 Results.- C.11 Extensions.- C.11.1 Extending ArbitraryCubes.- C.11.2 The Fanout Care Set and the Test Function.- D Precharged, Unate Circuits.