
VLSI Architectures for Future Video Coding
Maurizio Martina(Editor)
Institution of Engineering and Technology (Publisher)
Published on 7. October 2019
Book
Hardback
384 pages
978-1-78561-710-2 (ISBN)
Description
This book addresses future video coding from the perspective of hardware implementation and architecture design, with particular focus on approximate computing and the energy-quality scalability paradigm. Challenges in deploying VLSI architectures for video coding are identified and potential solutions postulated with reference to recent research in the field. The book offers systematic coverage of the designs, techniques and paradigms that will most likely be exploited in the design of VLSI architectures for future video coding systems.
Written by a team of expert authors from around the world, and brought together by an editor who is a recognised authority in the field, this book is a useful resource for academics and industry professionals working on VLSI implementation of video codecs.
Written by a team of expert authors from around the world, and brought together by an editor who is a recognised authority in the field, this book is a useful resource for academics and industry professionals working on VLSI implementation of video codecs.
More details
Series
Language
English
Place of publication
Stevenage
United Kingdom
Target group
College/higher education
Professional and scholarly
Product notice
sewn/stitched
Cloth over boards
Dimensions
Height: 236 mm
Width: 160 mm
Thickness: 23 mm
Weight
726 gr
ISBN-13
978-1-78561-710-2 (9781785617102)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Person
Maurizio Martina is an Associate Professor in the Electronics and Telecommunications Department at Politecnico di Torino, Italy. He conducts research in the field of VLSI architectures for multimedia signal processing and communications, particularly the design of image/video compression and iterative channel-code decoder architectures. He has published almost 100 papers in international journals and conferences. He is and has been in the technical program committee of several international conferences.
Editor
Associate ProfessorPolitecnico di Torino, Electronics and Telecommunications Department, Italy
Content
Chapter 1: Scalable transform architectures for video coding
Chapter 2: Joint algorithm-architecture design of video coding modules
Chapter 3: High-throughput architectures for high-resolution video coding: system architecture analysis
Chapter 4: High-throughput architectures for high-resolution video coding: hardwired oriented algorithms and VLSI architectures
Chapter 5: Low-power circuit design techniques for high-resolution video coding
Chapter 6: Real-time architectures for 3D video coding
Chapter 7: Frame memory compression for high-resolution video coding
Chapter 8: Discrete transform approximations for video coding
Chapter 9: Reconfigurable and approximate computing for video coding
Chapter 10: Future video coding: new tools and algorithms
Chapter 2: Joint algorithm-architecture design of video coding modules
Chapter 3: High-throughput architectures for high-resolution video coding: system architecture analysis
Chapter 4: High-throughput architectures for high-resolution video coding: hardwired oriented algorithms and VLSI architectures
Chapter 5: Low-power circuit design techniques for high-resolution video coding
Chapter 6: Real-time architectures for 3D video coding
Chapter 7: Frame memory compression for high-resolution video coding
Chapter 8: Discrete transform approximations for video coding
Chapter 9: Reconfigurable and approximate computing for video coding
Chapter 10: Future video coding: new tools and algorithms