Digital Design
3rd Edition
Published on 23. August 2001
Book
Mixed media product
516 pages
978-0-13-062121-4 (ISBN)
Description
This is a modern revision of the classic digital design textbook. The book teaches the basic tools for the design of digital circuits in a clear, easily accessible manner. New to This Edition: *Nine sections on Verilog Hardware Description Language (HDL) inserted in discrete sections, allowing the material to be covered or skipped as desired. The Verilog HDL presentation is at a suitable level for beginning students who are learning digital circuits for the first time. *Reorganized material on combinational circuits is now covered in a single chapter. *The emphasis in the sequential circuits chapters is now on design with D flip-flops instead of JK and SR flip-flops. *The material on memory and programmable logic is now consolidated in one chapter. *Chapter 8 consists mostly of new material and now covers digital design in the Register Transfer Level (P) FL), preparing the reader for more advanced design projects and further Verilog HDL studies. *A new section in Chapter 11 supplements the laboratory experiments with HDL experiments. These unable the reader to check the circuits designed in the laboratory by means of hardware components and/or by HDL simulation.*
Text accompanied by Verilog simulator software-SynaptiCAD's VeriLogger Pro evaluation version, a Verilog simulation environment that combines all of the features of a traditional Verilog simulator with a powerful graphical test vector generator. Fast model testing in VeriLogger Pro allows the reader to perform bottom-up testing of every model in a design. All of the HDL examples in the book can be found on the CD-ROM. *A Companion Website includes resources for instructors and students such as transparency masters of all figures in the book, all HDL code examples from the book, a Verilog tutorial, tutorials on using the VeriLogger Pro software, and more. It can be found at http://www.prenhall.com/mano
Text accompanied by Verilog simulator software-SynaptiCAD's VeriLogger Pro evaluation version, a Verilog simulation environment that combines all of the features of a traditional Verilog simulator with a powerful graphical test vector generator. Fast model testing in VeriLogger Pro allows the reader to perform bottom-up testing of every model in a design. All of the HDL examples in the book can be found on the CD-ROM. *A Companion Website includes resources for instructors and students such as transparency masters of all figures in the book, all HDL code examples from the book, a Verilog tutorial, tutorials on using the VeriLogger Pro software, and more. It can be found at http://www.prenhall.com/mano
More details
Edition
3rd edition
Language
English
Place of publication
United States
Publishing group
Pearson Education (US)
Target group
College/higher education
Dimensions
Height: 242 mm
Width: 191 mm
Thickness: 24 mm
Weight
1005 gr
ISBN-13
978-0-13-062121-4 (9780130621214)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
New editions
Book
02/2007
4th Edition
Pearson
€92.46
Article exhausted; check for reprint
Previous edition
M. Morris R. Mano
Verilog Simulator CD ROM
Software
07/2001
3rd Edition
Pearson
€18.27
Article exhausted; check for reprint
Content
1. Binary Systems.
Digital Systems. Binary Numbers. Number Base Conversions. Octal and Hexadecimal Numbers. Complements. Signed Binary Numbers. Binary Codes. Binary Storage and Registers. Binary Logic.
2. Boolean Algebra and Logic Gates.
Basic Definitions. Axiomatic Definition of Boolean Algebra. Basic Theorems and Properties of Boolean Algebra. Boolean Functions. Canonical and Standard Forms. Other Logic Operations. Digital Logic Gates. Integrated Circuits.
3. Gate-Level Minimization.
The Map Method. Four-Variable Map. Five-Variable Map. Product of Sums Simplification. Don't-Care Conditions. NAND and NOR Implementation. Other Two-Level Implementations. Exclusive-OR Function. HardwareDescriptionLanguage(HDL).
4. Combinational Logic.
Combinational Circuits. Analysis Procedure. Design Procedure. Binary Adder-Subtractor. Decimal Adder. Binary Multiplier. Magnitude Comparator. Decoders. Encoders. Multiplexers. HDLFor CombinationalCircuits.
5. Synchronous Sequential Logic.
Sequential Circuits. Latches. Flip-Flops. Analysis of Clocked Sequential Circuits. HDL For Sequential Circuits. State Reduction and Assignment. Design Procedure.
6. Registers ad Counters.
Registers. Shift Registers. Ripple Counters. Synchronous Counters. Other Counters. HDL for Registers and Counters.
7. Memory and Programmable Logic.
Introduction. Random-Access Memory. Memory Decoding. Error Detection and Correction. Read-Only Memory. Programmable Logic Array. Programmable Array Logic. Sequential Programmable Devices.
8. Register Transfer Level.
Register Transfer Level (RTL) Notation. Register Transfer Level in HDL. Algorithmic State Machines (ASM). Design Example. HDL Description of Design Example. Binary Multiplier. Control Logic. HDL Description of Binary Multiplier. Design With Multiplexers.
9. Asynchronous Sequential Logic.
Introduction. Analysis Procedure. Circuits With Latches. Design Procedure. Reduction of State and Flow Tables. Race-Free State Assignment. Hazards. Design Example.
10. Digital Integrated Circuits.
Introduction. Special Characteristics. Bipolar-Transistor Characteristics. RTL and DTL Circuits. Transistor-Transistor Logic (TTL). Emitter-Coupled Logic (ECL). Metal-Oxide Semiconductor (MOS). Complementary MOS (CMUS). CMOS Transmission Gate Circuits. Switch-Lever Modeling With HDL.
11. Laboratory Experiments.
Introduction to Experiments. Binary and Decimal Numbers. Digital Logic Gates. Simplification of Boolean Functions. Combinational Circuits. Code Converters. Design with Multiplexers. Adders and Subtractors. Flip-flops. Sequential Circuits. Counters. Shift Registers. Serial Addition. Memory Unit. Lamp Handball. Clock-Pulse Generator. Parallel Adder and Accumulator. Binary Multiplier. Asynchronous Sequential Circuits. Verilog HDL Simulation Experiments.
12. Standard Graphic Symbols.
Rectangular-Shape Symbols. Qualifying Symbols. Dependency Notation. Symbols For Combinational Elements. Symbols For Flip-Flops. Symbols For Registers. Symbols For Counters. Symbol For RAM.
Answers To Selected Problems.
Digital Systems. Binary Numbers. Number Base Conversions. Octal and Hexadecimal Numbers. Complements. Signed Binary Numbers. Binary Codes. Binary Storage and Registers. Binary Logic.
2. Boolean Algebra and Logic Gates.
Basic Definitions. Axiomatic Definition of Boolean Algebra. Basic Theorems and Properties of Boolean Algebra. Boolean Functions. Canonical and Standard Forms. Other Logic Operations. Digital Logic Gates. Integrated Circuits.
3. Gate-Level Minimization.
The Map Method. Four-Variable Map. Five-Variable Map. Product of Sums Simplification. Don't-Care Conditions. NAND and NOR Implementation. Other Two-Level Implementations. Exclusive-OR Function. HardwareDescriptionLanguage(HDL).
4. Combinational Logic.
Combinational Circuits. Analysis Procedure. Design Procedure. Binary Adder-Subtractor. Decimal Adder. Binary Multiplier. Magnitude Comparator. Decoders. Encoders. Multiplexers. HDLFor CombinationalCircuits.
5. Synchronous Sequential Logic.
Sequential Circuits. Latches. Flip-Flops. Analysis of Clocked Sequential Circuits. HDL For Sequential Circuits. State Reduction and Assignment. Design Procedure.
6. Registers ad Counters.
Registers. Shift Registers. Ripple Counters. Synchronous Counters. Other Counters. HDL for Registers and Counters.
7. Memory and Programmable Logic.
Introduction. Random-Access Memory. Memory Decoding. Error Detection and Correction. Read-Only Memory. Programmable Logic Array. Programmable Array Logic. Sequential Programmable Devices.
8. Register Transfer Level.
Register Transfer Level (RTL) Notation. Register Transfer Level in HDL. Algorithmic State Machines (ASM). Design Example. HDL Description of Design Example. Binary Multiplier. Control Logic. HDL Description of Binary Multiplier. Design With Multiplexers.
9. Asynchronous Sequential Logic.
Introduction. Analysis Procedure. Circuits With Latches. Design Procedure. Reduction of State and Flow Tables. Race-Free State Assignment. Hazards. Design Example.
10. Digital Integrated Circuits.
Introduction. Special Characteristics. Bipolar-Transistor Characteristics. RTL and DTL Circuits. Transistor-Transistor Logic (TTL). Emitter-Coupled Logic (ECL). Metal-Oxide Semiconductor (MOS). Complementary MOS (CMUS). CMOS Transmission Gate Circuits. Switch-Lever Modeling With HDL.
11. Laboratory Experiments.
Introduction to Experiments. Binary and Decimal Numbers. Digital Logic Gates. Simplification of Boolean Functions. Combinational Circuits. Code Converters. Design with Multiplexers. Adders and Subtractors. Flip-flops. Sequential Circuits. Counters. Shift Registers. Serial Addition. Memory Unit. Lamp Handball. Clock-Pulse Generator. Parallel Adder and Accumulator. Binary Multiplier. Asynchronous Sequential Circuits. Verilog HDL Simulation Experiments.
12. Standard Graphic Symbols.
Rectangular-Shape Symbols. Qualifying Symbols. Dependency Notation. Symbols For Combinational Elements. Symbols For Flip-Flops. Symbols For Registers. Symbols For Counters. Symbol For RAM.
Answers To Selected Problems.