Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures
Description
This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications.
- Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems;
- Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems;
- Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.
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Persons
Kanchan Manna is currently an assistant professor in Department of Computer Science and Engineering, Indian Institute of Technology (IIT) Patna, India. Prior to this, he has worked as a post-doctoral scientist in the Department of Electrical and Computer Engineering (ECE) at George Washington University (GWU), Washington-DC, USA. He earned the MS degree in information technology from Indian Institute of Technology (IIT) Kharagpur, India and the PhD degree in computer science engineering from IIT Kharagpur. His current research interests include Network-on-Chip (NoC) based multicore architecture design, performance and cost evaluation, application mapping in 2D and 3D environments, including thermal-safety, reliability, fault-tolerant and testing.
Jimson Mathew is currently an associate professor and head of the Computer Science and Engineering Department, Indian Institute of Technology (IIT) Patna, India. He is also honorary visiting fellow at the Department of Computer Science and Engineering, University of Bristol, UK. He received the Masters in Computer engineering from Nanyang Technological University, Singapore and the Ph.D. degree in computer engineering from the University of Bristol, Bristol, U.K. Prior to this, he has worked with the Centre for Wireless Communications, National University of Singapore, Bell Laboratories Research Lucent Technologies North Ryde, Australia, Royal Institute of Technology KTH, Stockholm, Sweden and Department of Computer Science, University of Bristol, UK. His research interests include fault-tolerant computing, computer arithmetic, hardware security, very large scale integration design and design automation, and design of Network on Chip Architectures. He is the co-author of three published books, and close to 100 publications in international journals and conferences of repute.
Content
Introduction to Network-on-Chip Designs and Tests.- Iterative Mapping with Through Silicon Via (TSV) placement for 3D-NoC-based multicore systems.- A constructive Heuristic for integrated mapping and TSV Placement for 3D-NoC-based multicore systems.- Discrete Particle Swarm Optimization for integrated mapping and TSV Placement for 3D-NoC-based multicore systems.- Temperature-aware application mapping strategy for 2D-NoC-based multicore systems.- Temperature-aware design strategy for 3D-NoC-based multicore systems.- Temperature-aware test strategy for 2D as well as 3D-NoC-based multicore systems.