Machine Learning Systems
Description
This book addresses the technological contributions and developments of advanced hardware for Machine Learning (ML) computing systems. The authors discuss state-of-the-art progress in this area (and related topics) as well as reporting on their application to diverse fields. This is achieved by chapters covering the entire spectrum of research activities to include design and applications, with a focus on high performance and dependable operation. The entire hardware stack (from circuit, to architecture, up to the system level) is discussed in detail. The book will cover innovative material as well as tutorials, reviews and surveys of current theoretical/experimental results, design methodologies and applications over a wide spectrum of scope for an enlarged readership, so to include engineers as well as scientists.
- Discusses a wide range of topics for Machine Learning-based computer systems;
- Covers design and application for the entire hardware stack, with a focus on high performance and dependability;
- Includes innovative material, as well as tutorials, reviews and surveys of current theoretical/experimental results.
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Shanshan Liu received the Ph.D. degree in Microelectronics and Solid-State Electronics from Harbin Institute of Technology, Harbin, China, in 2018. She was a post-doctoral researcher with the Department of Electrical and Computer Engineering, Northeastern University, Boston, USA, from 2018 to 2021, and an assistant professor with the Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, USA from 2021 to 2023. She is currently a professor with the School of Information and Communication Engineering, University of Electronic Science and Technology of China, Chengdu, China.Dr. Liu is an Associate Editor for the IEEE Transactions on Emerging Topics in Computing and the IEEE Transactions on Nanotechnology and serves as a technical program committee member for several IEEE/ACM conferences such as NANO, DFT, GLSVLSI. She is also the 2024-elected Member-at-Large of the IEEE Nanotechnology Council. Her research interests include fault tolerance design in high performance computing systems, emerging computing, VLSI design, dependable machine learning, and error correction codes.
Pedro Reviriego completed the PhD in 1997 and joined the R&D department of Teldat a Spanish company that designs and manufactures routers. Then in 2000, he moved on to an Irish a start-up that was developing Ethernet transceiver ASICs and that later was acquired by an US company (now part of Broadcom). The transceivers developed were licensed to Intel and had a large commercial success. Since 2007 he has been in Academia with positions at Nebrija University, Universidad Carlos III de Madrid and currently Universidad Politécnica de Madrid.Pedro Reviriego has made significant contributions in different areas like Energy Efficiency in Ethernet on which he was a pioneer contributing to the IEEE 802.3 standards and writing seminal papers on the field with more than 470 citations in Google Scholar. This work was recognized with two Google Research Awards. The second topic on which he has worked is the design and implementation of Error Correction Codes (ECCs) to protect memories. In this area, he has pioneered the use of one step majority logic decodable codes for memory protection with a large number of publications. More recently, he focuses on fault-tolerant machine learning, in this area he has proposed fault tolerant implementations for many machine learning algorithms including complex neural networks.Pedro Reviriego is associate editor of IEEE Transactions on Emerging Topics in Computing and has published more than 300 papers on journals indexed on the JCR, most of them in Transactions of the IEEE and more than 5900 citations on Google Scholar. He also holds more than 12 US patents most of them in collaboration with NVIDIA/Mellanox.
Zhen Gao received the BS, MS and PhD degree in Electrical Engineering from Tianjin University, China, in 2005, 2007 and 2011, respectively. He was a visiting scholar in GeorgiaTech during 2008 ~ 2010, and a Postdoc researcher in Tsinghua University during 2011 ~ 2014. He is currently an Associate Professor in Tianjin University. His research interests include circuit reliability, fault tolerance design, wireless communications and blockchain technologies.
Fabrizio Lombardi graduated in 1977 from the University of Essex (UK) with a B.Sc. (Hons.) in Electronic Engineering. In 1977 he joined the Microwave Research Unit at University College London, where he received the Master in Microwaves and Modern Optics (1978), the Diploma in Microwave Engineering (1978) and the Ph. D. from the University of London (1982). He is currently the holder of the International Test Conference (ITC) Endowed Chair at Northeastern University, Boston. Currently, Dr. Lombardi is the 2022-2023 President; of the IEEE Nanotechnology Council (NTC); in 2021 he was 2nd VP of the IEEE Computer Society (CS). He was the VP of Publications of the IEEE CS (2019-2020) and the NTC (2020) as well as also a member of the IEEE Publication Services and Products Board (PSPB) (2019-2023). He has been appointed on Executive Boards of many non-profit organizations (such as Computing-in-the-Core, now code.org the non-partisan advocacy coalition for K-12 Computer Science education) as well as the Computer Society (as an elected two-term member of its Board of Governors (2012-2017)) and the IEEE (as an appointed member of the Future Directions Committee (2014-2017)).In the past Dr. Lombardi has been a two 2-year term Editor-in-Chief (2007-2010), Associate Editor-in-Chief (2000-2006) and Associate Editor (1996-2000) of the IEEE Transactions on Computers, the inaugural two-term Editor-in-Chief of the IEEE Transactions on Emerging Topics in Computing (2013-2017); Editor-in-Chief of the IEEE Transactions on Nanotechnology (2014-2019) as well as member of the Editorial Boards of the ACM Journal of Emerging Technologies in Computing Systems, the IEEE Design & Test Magazine and IEEE Transactions on CAD of ICAS. Dr. Lombardi has been twice a Distinguished Visitor of the IEEE Computer Society (1990-1993 and 2001-2004). He serves as Chair of the Committee on "Nanotechnology Devices and Systems" of the Test Technology Technical Council of the IEEE.Dr. Lombardi is a Fellow of the IEEE for "contributions to testing and fault tolerance of digital systems". He was the recipient of the 2011 Meritorious Service Award and elevated to Golden Core membership in the same year by the IEEE CS; he was the Chair of the 2016 and 2017 IEEE CS Fellow Evaluation Committee. He has been awarded the 2019 NTC Distinguished Service Award, the 2019 "Spirit of the CS" Award and the 2021 T Michael Elliott Distinguished Service Certificate from the CS. He has received many professional awards: the Visiting Fellowship at the British Columbia Advanced System Institute, University of Victoria, Canada (1988), twice the Texas Experimental Engineering Station Research Fellowship (1991-1992, 1997-1998) the Halliburton Professorship (1995), the Outstanding Engineering Research Award at Northeastern University (2004) and an International Research Award from the Ministry of Science and Education of Japan (1993-1999). Dr. Lombardi was the recipient of the 1985/86 Research Initiation Award from the IEEE/Engineering Foundation and a Silver Quill Award from Motorola-Austin (1996). Together with his students, his manuscripts have been selected for the best paper awards at technical events/meetings such as IEEE DFT and IEEE/ACM Nanoarch. Since inception, he has been always included in the list of World's Top 2% Scientists, as compiled by Stanford University.Dr. Lombardi has been involved in organizing many international symposia, conferences and workshops sponsored by professional organizations as well as guest editor of Special Issues in archival journals and magazines. His research interests are emerging technologies (mostly nanoscale circuits and magnetic devices), memory systems, VLSI design and fault/defect tolerance of digital systems. He has extensively published in these areas and coauthored/edited eleven books.
Content
High performance machine learning accelerators on fpga.- Floating point arithmetic in deep neural networks evaluation and implementation of conventional and emerging formats with mixed precision strategies.- High performance computing architectures for ml.- High performance domain specific computing architectures for machine learning.- Edge ai training accelerator design.- Accelerating machine learning with unconventional architectures.- Mram based energy efficient computing architectures for machine learning accelerators.- Energy efficient data aware computation in computing in memory architecture.- Stochastic computing applied to morphological neural networks.- Approximate computing in machine learning - More than you bargained for.- Edge computing meets giant ai innovations in large language model efficiency.- Chiplet based accelerator design for scalable training of transformer based generative adversarial networks.- Energy consumption in generative ai insights from large language models inference.- Towards sustainable and responsible gen ai an investigation on energy efficient computing and cost effective complementary components.- Low power machine learning realization techniques on biomedical wearable devices.- Application of algorithm and hardware co design in the hardware accelerator of visual slam front end.- Application of Aagorithm and hardware co design in the hardware accelerator of visual slam back end.- Hardware efficient designs for spiking neural networks.- Understanding neural network fault tolerance from the analog hardware to the gpu.- On the use of ml techniques in safety critical systems.- Fault injection and tolerance techniques for deep learning models deployed on sram based fpgas.- Dependability evaluation of parameters and variables in large language models llms to soft errors on memory.- Lightweight algorithm based fault tolerance abft for resilient ml systems.- Using error correction code schemes in dependable machine learning systems.- Analog error correcting codes for dependable in memory computing of neural networks.- Perturbation based error tolerance for large scale networks.- Quantization aided cost efficient reliability of cnn accelerators for edge ai.- Trustworthy ai at the cloud.- Exploring hardware driven privacy techniques for trustworthy machine learning.- Machine learning and hardware security the role of ai for hardware in the security era.- Machine learning systems for high performance and dependability the role of fpga design.