Algorithms and Architectures for Parallel Processing
Description
The eight volume set, LNCS 16381-16388 constitutes the refereed proceedings of the 25th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2025, held in Zhengzhou, China, during October 30 -November 2, 2025.
The 158 full papers, 104 research papers and 48 session papers included in these proceedings were carefully reviewed and selected from 543 submissions. They focus on the following topical sections:
Part I : Parallel and Distributed Architectures; Software Systems and Programming Models.
Part II : Parallel and Distributed Algorithms and Applications.
Part III : Parallel and Distributed Algorithms and Applications; Internet of Things and Cyber-Physical-Social Computing; Performance Modeling and Evaluation.
Part IV : Service Dependability and Security in Distributed and Parallel Systems; Network Architectures and Algorithms.
Part V: Network Architectures and Algorithms.
Part VI: Parallel and Distributed Architectures; Software Systems and Programming Models; Parallel and Distributed Algorithms and Applications; Big Data Management and Analysis; Performance Modeling and Evaluation.
Part VII: Service Dependability and Security in Distributed and Parallel Systems; Network Architectures and Algorithms; Internet of Things and Cyber-Physical-Social Computing.
Part VIII: Intelligent Distributed Computing; Resource Coordination and Joint Optimization in Cloud-Edge-End Systems; Symbiotic AI and Data Ecosystems; Smart Education Powered by Parallel and Distributed Processing; AI for Networks and Networking for AI; Emerging Network Technologies in Computing and Networking Convergence.
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Content
.- Parallel and Distributed Architectures.
.- Streamline: A High-Parallelized BFT Consensus Protocol for Blockchain.
.- PliKOS: Pre-Warming Serverless Functions under Pulsed Loads.
.- VPFU: A Bit-Serial Architecture for Energy-Efficient Acceleration of Ultra-Low Precision DNNs.
.- 3D-DP: A Practical DRL-Based Data Prefetcher with a Dynamic Prefetch Degree and Direction.
.- HRE-Store: A Hierarchical and Scalable Storage Architecture for Permissioned Blockchains.
.- Reputation-Based Secure Node Allocation and Dynamic Monitoring for Blockchain Sharding.
.- A Parallel Implementation of ChaCha20 on MT-3000 Heterogeneous Multi-Zone Processor.
.- INF-DRAM: An In-Memory Prefetching DRAM Architecture.
.- PQIns: Pipeline-Driven Application-Specific Instruction-Set Architecture for Hybrid Post-Quantum Cryptography Acceleration.
.- Federated Incremental Learning Method Based on Memory Replay and Self-Distillation Technology.
.- SpikeEAR: Low-Power Neuromorphic Auditory System for Real-Time Scene Analysis on FPGA .
.- KiRa: A Unified Memory Architecture for Efficient Post-Quantum Cryptographic Algorithms.
.- A GCN Accelerator with Unified Architecture.
.- ACIM: Approximate Computing Based Ising Machine with Dynamic-ratio Parallel Annealing.
.- Jarm: Automated Remote Memory System for Java Applications.
.- Distributed Energy-Efficient Trajectory Optimization for Multi-UAV Based Agricultural Field Sensing.
.- Chameleon Hash-Based Redactable Blockchains: A Systematic Literature Review.
.- GP-BFT: A Low-Latency BFT Protocol under Grouped Multi-Committee Parallel Consensus.
.- EncloPC: Power Control for Server Enclosures with Heterogeneous Workloads at Power Peaks .
.- Updatable Verifiable Credential Sharing with Selective Disclosure.
.- SecureIMR: A Plausibly Deniable Storage System for Interlaced Magnetic Recording.
.- Heterogeneous Parallel Optimization Research of Plasma Guiding Center Orbit Simulation.
.- Facess: A Fast Access Method for Shared Data Among Multi-Cores in Parallel Programs.
.- A Mapping Strategy Optimization Framework for Systolic Array Accelerators.
.- LFBC: A Lifecycle-Managed False Bubble Flow Control Scheme for Torus Networks.
.- STREAM: A Transparent Reordering Engine for High-Performance Zoned Namespace SSDs.
.- Weight-and-Load-Driven Approximation Methodology for Energy-Efficient Neural Network Accelerators.
.- HT-DLC: A Data Layout and Computing Design for Logic-in-Memory Convolution with High Throughput.
.- Software Systems and Programming Models.
.- GRIS: A Graph Neural Network-Based Reinforcement Learning Approach for Instruction Scheduling.
.- Tiling-Aware Vectorization Framework for Perfect Loop Nests in MLIR.
.- MLog: Achieving Low-Latency, Scalable Shared Log Writes via RDMA Multicast Protocol.
.- Sumeru: An Efficient Hybrid-Granularity Cache Management Scheme for CXL-SSDs.