
Principles of Verifiable RTL Design
A functional coding style supporting verification processes in Verilog
Kluwer Academic Publishers
2nd Edition
Published on 31. May 2001
Book
Hardback
XXIV, 282 pages
978-0-7923-7368-1 (ISBN)
Description
System designers, computer scientists and engineers have c- tinuously invented and employed notations for modeling, speci- ing, simulating, documenting, communicating, teaching, verifying and controlling the designs of digital systems. Initially these s- tems were represented via electronic and fabrication details. F- lowing C. E. Shannon's revelation of 1948, logic diagrams and Boolean equations were used to represent digital systems in a fa- ion that de-emphasized electronic and fabrication detail while revealing logical behavior. A small number of circuits were made available to remove the abstraction of these representations when it was desirable to do so. As system complexity grew, block diagrams, timing charts, sequence charts, and other graphic and symbolic notations were found to be useful in summarizing the gross features of a system and describing how it operated. In addition, it always seemed necessary or appropriate to augment these documents with lengthy verbal descriptions in a natural language. While each notation was, and still is, a perfectly valid means of expressing a design, lack of standardization, conciseness, and f- mal definitions interfered with communication and the understa- ing between groups of people using different notations. This problem was recognized early and formal languages began to evolve in the 1950s when I. S. Reed discovered that flip-flop input equations were equivalent to a register transfer equation, and that xvi tor-like notation. Expanding these concepts Reed developed a no- tion that became known as a Register Transfer Language (RTL).
More details
Edition
2nd ed. 2001
Language
English
Place of publication
New York
United States
Target group
Professional and scholarly
Research
Edition type
Revised edition
Illustrations
XXIV, 282 p.
Dimensions
Height: 241 mm
Width: 160 mm
Thickness: 22 mm
Weight
638 gr
ISBN-13
978-0-7923-7368-1 (9780792373681)
DOI
10.1007/b116575
Schweitzer Classification
Other editions
Additional editions

Lionel Bening | Harry D. Foster
Principles of Verifiable RTL Design
A functional coding style supporting verification processes in Verilog
Book
03/2013
2nd Edition
Springer
€160.49
Shipment within 15-20 days

Lionel Bening | Harry D. Foster
Principles of Verifiable RTL Design
A functional coding style supporting verification processes in Verilog
E-Book
05/2007
2nd Edition
Kluwer Academic Publishers
€149.79
Available for download
Content
The Verification Process.- Coverage, Events and Assertions.- RTL Methodology Basics.- RTL Logic Simulation.- RTL Formal Verification.- Verifiable RTL Style.- The Bad Stuff.- Verifiable RTL Tutorial.- Principles of Verifiable RTL Design.