Designing Digital Computer Systems with Verilog
Published on 2. December 2004
Book
Hardback
176 pages
978-0-521-82866-6 (ISBN)
Description
This book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers.
More details
Language
English
Place of publication
Cambridge
United Kingdom
Target group
Professional and scholarly
College/higher education
Illustrations
5 Tables, unspecified
Dimensions
Height: 260 mm
Width: 183 mm
Thickness: 14 mm
Weight
538 gr
ISBN-13
978-0-521-82866-6 (9780521828666)
Copyright in bibliographic data and cover images is held by Nielsen Book Services Limited or by the publishers or by their respective licensors: all rights reserved.
Schweitzer Classification
Other editions
Additional editions
David J. Lilja | Sachin S. Sapatnekar
Designing Digital Computer Systems with Verilog
Book
11/2007
Cambridge University Press
€79.60
Shipment within 15-20 days
David J. Lilja | Sachin S. Sapatnekar
Designing Digital Computer Systems with Verilog
E-Book
01/2007
1st Edition
Cambridge University Press
€52.99
Available for download
Persons
DAVID LILJA received his PhD in Electrical Engineering from the University of Illinois at Urbana-Champaign. He is currently a Professor of Electrical and Computer Engineering , and a Fellow of the Minnesota Supercomputing Institute, at the University of Minnesota in Minneapolis. He also serves as a member of the graduate faculties in Computer Science and Scientific Computation, and was the founding Director of Graduate Studies for Computer Engineering. He has served on the program committees of numerous conferences and as associate editor for IEEE Transactions on Computers. David is a Senior member of the IEEE and a member of the ACM. SACHIN SAPATNEKAR received his PhD from the University of Illinois at Urbana-Champaign. Currently, he is the Robert and Marjorie Henle Professor in the Department of Electrical and Computer Engineering at the University of Minnesota, and serves on the graduate faculty in Computer Science and Engineering. He has served as Associate Editor for several IEEE journals, a distinguished visitor for the IEEE Computer Society and a distinguished lecturer for the IEEE Circuits and Systems Society. He is a recipient of the NSF Career Award and the SRC Technical Excellence Award. He is a Fellow of the IEEE and a member of the ACM.
Content
Preface; 1. Controlling complexity; 2. A verilogical place to start; 3. Defining the instruction set architecture; 4. Algorithmic behavioral modeling; 5. Building an assembler for VeSPA; 6. Pipelining; 7. Implementation of the pipelined processor; 8. Verification; Appendix A: the VeSPA instruction set architecture (ISA); Appendix B: the VASM assembler; Index.